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19
SPI
19.1
SPi Module Overview
The S1C17624/604/622/602/621 includes a synchronized serial interface module (SPI).
The following shows the main features of the SPI:
• Number of channels: 1 channel
• Supports both master and slave modes.
• Data length: 8 bits fixed
• Supports both MSB first and LSB first modes.
• Contains one-byte receive data buffer and one-byte transmit data buffer.
• Supports full-duplex communications.
• Data transfer timing (clock phase and polarity variations) is selectable from among 4 types.
• Can generate receive buffer full and transmit buffer empty interrupts.
Figure 19.1.1 shows the SPI module configuration.
Internal bus
ITC
PCLK
T16 Ch.1
output clock
notes: • In the S1C17602/621, the transmit buffer empty interrupt can only be used in master mode.
In the S1C17624/604/622, the transmit buffer empty interrupt can be used in both master and
slave modes.
• The letter 'x' in register and pin names refers to a channel number (0).
Example: SPI_CTLx register
Ch.0: SPI_CTL0 register
19.2
SPi input/Output Pins
Table 19.2.1 lists the SPI pins.
Pin name
i/O
SDI0 (Ch.0)
I
SDO0 (Ch.0)
O
S1C17624/604/622/602/621 TeChniCal Manual
Receive data
buffer (1 byte)
Bus I/F
and
control
registers
Transmit data
Interrupt
buffer (1 byte)
control
1/4
Figure 19.
1.1 SPI Module Configuration
Table 19.
2.1 List of SPI Pins
Qty
1
SPI data input pin
Inputs serial data from SPI bus.
1
SPI data output pin
Outputs serial data to SPI bus.
Seiko epson Corporation
Shift register
Clock/transfer control
Shift register
SPI Ch.x
Function
19 SPi
SDIx
SPICLKx
#SPISSx
SDOx
19-1
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