Epson S1C17624 Technical Manual page 195

18 uaRT
D0 TDBe: Transmit Data Buffer empty Flag Bit
Indicates the transmit data buffer status.
1 (R): Buffer empty (default)
0 (R): Data exists
TDBE is reset to 0 when transmit data is written to the transmit data buffer and is set to 1 when the data
is transferred to the shift register.
uaRT Ch.x Transmit Data Registers (uaRT_TXDx)
Register name address Bit
uaRT Ch.x 0x4101 D7–0 TXD[7:0]
Transmit Data 0x4121
Register
(8 bits)
(uaRT_TXDx)
D[7:0] TXD[7:0]: Transmit Data
Write transmit data to be set in the transmit data buffer. (Default: 0x0)
The UART starts transmitting when data is written to this register. Data written to TXD[7:0] is retained
until sent to the transmit data buffer. Transmitting data from within the transmit data buffer generates a
cause of transmit buffer empty interrupt.
TXD7 (MSB) is invalid in 7-bit mode.
Serial converted data is output from the SOUTx pin beginning with the LSB, in which the bits set to 1
are output as High level and bits set to 0 as Low level signals.
This register can also be read.
uaRT Ch.x Receive Data Registers (uaRT_RXDx)
Register name address Bit
uaRT Ch.x 0x4102 D7–0 RXD[7:0]
Receive Data 0x4122
Register (8 bits)
(uaRT_RXDx)
D[7:0] RXD[7:0]: Receive Data
Data in the receive data buffer is read out in sequence, starting with the oldest. Received data is placed in
the receive data buffer. The receive data buffer is a 2-byte FIFO that allows proper data reception until it
fills, even if data is not read out. If the buffer is full and the shift register also contains received data, an
overrun error will occur, unless the data is read out before reception of the subsequent data starts.
The receive circuit includes two receive buffer status flags: RDRY/UART_STx register and RD2B/
UART_STx register. The RDRY flag indicates the presence of valid received data in the receive data
buffer, while the RD2B flag indicates the presence of two received data in the receive data buffer.
A receive buffer full interrupt occurs when the received data in the receive data buffer reaches the num-
ber specified by RBFI/UART_CTLx register.
0 is loaded into RXD7 in 7-bit mode.
Serial data input via the SINx pin is converted to parallel, with the initial bit as LSB, the High level bit
as 1, and the Low level bit as 0. This data is then loaded into the receive data buffer.
This register is read-only. (Default: 0x0)
uaRT Ch.x Mode Registers (uaRT_MODx)
Register name address Bit
uaRT Ch.x 0x4103 D7–5 –
Mode Register 0x4123
D4
(uaRT_MODx)
(8 bits)
D3
D2
D1
D0
D[7:5] Reserved
18-10
name Function
Transmit data
TXD7(6) = MSB
TXD0 = LSB
name Function
Receive data in the receive data
buffer
RXD7(6) = MSB
RXD0 = LSB
name Function
reserved
Chln Character length select
PRen
Parity enable
PMD
Parity mode select
STPB Stop bit select
SSCK
Input clock select
Seiko epson Corporation
Setting init. R/W
0x0 to 0xff (0x7f) 0x0 R/W
Setting init. R/W
0x0 to 0xff (0x7f) 0x0
Setting init. R/W
–
1 8 bits 0 7 bits
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 External 0 Internal
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
Remarks
R Older data in the buf-
fer is read out first.
Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W