Epson S1C17624 Technical Manual page 230

• When the asynchronous address detection function is enabled, data transfer cannot be per-
formed even if the PCLK frequency is eight-times or higher than the transfer rate. Be sure to
disable the asynchronous address detection function during normal operation.
D0 COM_MODe: i
Enables or disables data communication.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set COM_MODE to 1 to enable data communication after setting I2CSEN to 1 to enable I2CS opera-
tion. When COM_MODE is 0 (default), the I2CS module does not send back a response if the master
has sent the slave address of this module (it is regarded as that the I2CS module has returned a NAK to
the master).
i 2 C Slave Status Register (i2CS_STaT)
Register name address Bit
i 2 C Slave 0x4368 D15–8 –
Status Register
(16 bits)
D7
(i2CS_STaT)
D6
D5
D4
D3
D2
D1
D0
D[15:8] Reserved
D7 BSTaT: Bus Status Transition Bit
Indicates transition of the bus status.
1 (R): Changed
0 (R): Unchanged (default)
When one of the TXUDF/RXOVF, BFREQ, DMS, ASDET, DA_NAK, and DA_STOP bits is set to
1, BSTAT is also set to 1 and an interrupt signal is output to the ITC if the interrupt is enabled with
BSTAT_IEN/I2CS_ICTL register. This interrupt can be used to perform an error or terminate handling.
BSTAT will be reset to 0 when the TXUDF/RXOVF, BFREQ, DMS, ASDET, DA_NAK, and DA_
STOP bits are all reset to 0.
D6 Reserved
D5 TXuDF: Transmit Data underflow Bit (for transmission)
RXOVF: Receive Data Overflow Bit (for reception)
Indicates the transmit/receive data register status.
1 (R/W): Data underflow/overflow has been occurred
0 (R/W): Data underflow/overflow has not been occurred (default)
This bit is effective during transmission/reception when the clock stretch function is disabled. If a data
transmission begins before transmit data is written to the I2CS_TRNS register, it is regarded as a trans-
mit data underflow and TXUDF is set to 1. If the next data reception has completed before the received
data is read from the I2CS_RECV register and the I2CS_RECV register value is overwritten with the
newly received data, it is regarded as a data overflow and RXOVF is set to 1.
At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN/
I2CS_ICTL register. This interrupt can be used to perform an error handling.
After TXUDF/RXOVF is set to 1, it is reset to 0 by writing 1.
D4 BFReQ: Bus Free Request Bit
Indicates the I
1 (R/W): Request has been issued
0 (R/W): Request has not been issued (default)
S1C17624/604/622/602/621 TeChniCal Manual
2 C Slave Communication Mode Bit
name Function
reserved
BSTaT
Bus status transition
–
reserved
TXuDF Transmit data underflow
RXOVF Receive data overflow
BFReQ
Bus free request
DMS
Output data mismatch
aSDeT Async. address detection status
Da_naK NAK receive status
Da_STOP
STOP condition detect
2
C bus free request input status.
Seiko epson Corporation
Setting init. R/W
–
1 Changed 0 Unchanged
–
1 Occurred 0 Not occurred
1 Occurred 0 Not occurred
1 Error 0 Normal
1 Detected 0 Not detected
1 NAK 0 ACK
1 Detected 0 Not detected
2
21 i C SlaVe (i2CS)
Remarks
– – 0 when being read.
0 R
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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