Table of Contents
Advertisement
9 i/O PORTS (P)
note: The PxIMSK registers are available only for P0 and P1 ports.
D[7:0]
Pxie[7:0]: Px[7:0] Port interrupt enable Bits
Enables or disables each port interrupt.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting PxIEy to 1 enables the corresponding Pxy port input interrupt, while setting to 0 disables the in-
terrupt. Status changes for the input pins with interrupt disabled do not affect interrupt occurrence.
Px Port interrupt edge Select Registers (Px_eDGe)
Register name address
Bit
Px Port
0x5206
D7–0 PxeDGe[7:0] Px[7:0] port interrupt edge select
interrupt edge
0x5216
Select Register
(8 bits)
(Px_eDGe)
note: The PxEDGE registers are available only for P0 and P1 ports.
D[7:0]
PxeDGe[7:0]: Px[7:0] Port interrupt edge Select Bits
Selects the input signal edge for generating each port interrupt.
1 (R/W): Falling edge
0 (R/W): Rising edge (default)
Port interrupts are generated at the input signal falling edge when PxEDGEy is set to 1 and at the rising
edge when set to 0.
Px Port interrupt Flag Registers (Px_iFlG)
Register name address
Bit
Px Port
0x5207
D7–0 PxiF[7:0]
interrupt Flag
0x5217
Register
(8 bits)
(Px_iFlG)
note: The PxIFLG registers are available only for P0 and P1 ports.
D[7:0]
PxiF[7:0]: Px[7:0] Port interrupt Flag Bits
These are interrupt flags indicating the interrupt cause occurrence status.
1 (R):
Interrupt cause occurred
0 (R):
No interrupt cause occurred (default)
1 (W):
Reset flag
0 (W):
Ignored
PxIFy is the interrupt flag corresponding to the individual 16 ports of P0 and P1 and is set to 1 at the
specified edge (rising or falling edge) of the input signal. When the corresponding PxIEy/Px_IMSK
register has been set to 1, a port interrupt request signal is also output to the ITC at the same time. An
interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied.
PxIFy is reset by writing 1.
notes: • The P port module interrupt flag PxIFy must be reset in the interrupt handler routine after a
port interrupt has occurred to prevent recurring interrupts.
• To prevent generating unnecessary interrupts, reset the relevant PxIFy before enabling in-
terrupts for the required port using PxIEy/Px_IMSK register.
9-10
name
Function
name
Function
Px[7:0] port interrupt flag
Seiko epson Corporation
Setting
init. R/W
1 Falling edge 0 Rising edge
Setting
init. R/W
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
0
R/W
Remarks
0
R/W Reset by writing 1.
Advertisement
Table of Contents
