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ReMC interrupt Control Register (ReMC_inT)
Register name address
Bit
ReMC interrupt
0x5346
D15–11 –
Control Register
(16 bits)
D10
(ReMC_inT)
D9
D8
D7–3 –
D2
D1
D0
This register controls the data length counter underflow, input signal rising edge, and input signal falling edge inter-
rupts. The interrupt flag is set to 1 when the data length counter underflows, or when an input signal rising edge or
falling edge is detected. If the corresponding interrupt enable bit has been set to 1, the REMC outputs an interrupt
request signal to the ITC at the same time. An interrupt will be generated if the ITC and S1C17 Core interrupt con-
ditions are met. When an REMC interrupt occurs, check the interrupt flag status in this register to identify the cause
of interrupt occurred. If the interrupt enable bit is set to 0, the interrupt is disabled.
notes: • To prevent interrupt recurrences, the REMC module interrupt flag must be reset in the inter-
rupt handler routine after an REMC interrupt has occurred.
• To prevent generating unnecessary interrupts, reset the interrupt flag before enabling inter-
rupts by the interrupt enable bit.
D[15:11] Reserved
D10
ReMFiF: Falling edge interrupt Flag Bit
Indicates the falling edge interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
REMFIF is set to 1 at the input signal falling edge. REMFIF is reset to 0 by writing 1.
D9
ReMRiF: Rising edge interrupt Flag Bit
Indicates the rising edge interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
REMRIF is set to 1 at the input signal rising edge. REMRIF is reset to 0 by writing 1.
D8
ReMuiF: underflow interrupt Flag Bit
Indicates the underflow interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
REMUIF is set to 1 when a data length counter underflow occurs. REMUIF is reset to 0 by writing 1.
D[7:3]
Reserved
D2
ReMFie: Falling edge interrupt enable Bit
Enables or disables input signal falling edge interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
S1C17624/604/622/602/621 TeChniCal Manual
name
Function
reserved
ReMFiF
Falling edge interrupt flag
ReMRiF
Rising edge interrupt flag
ReMuiF
Underflow interrupt flag
reserved
ReMFie
Falling edge interrupt enable
ReMRie
Rising edge interrupt enable
ReMuie
Underflow interrupt enable
Seiko epson Corporation
22 iR ReMOTe COnTROlleR (ReMC)
Setting
init. R/W
–
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
22-9
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