Epson S1C17624 Technical Manual page 157

13 16-BiT PWM TiMeRS (T16a2)
T16a Counter Ch.x Control Registers (T16a_CTlx)
Register name address Bit
T16a Counter 0x5400 D15–7 –
Ch.x Control 0x5420
D6
Register (16 bits) D5–4 CCaBCnT
(T16a_CTlx)
D3
D2
D1
D0
D[15:7] Reserved
D6 hCM: half Clock Mode enable Bit
Sets T16A2 to half clock mode.
1 (R/W): Enabled (half clock mode)
0 (R/W): Disabled (normal clock mode) (default)
Setting HCM to 1 places T16A2 into half clock mode. In half clock mode, T16A2 uses the dual-edge
counter, which counts at the rising and falling edges of the count clock, to generate a compare A signal
when the dual-edge counter value matches the T16A_CCAx register. This makes it possible to control
the duty ratio with double accuracy as compared to normal clock mode.
Setting HCM to 0 places T16A2 into normal clock mode. In normal clock mode, T16A2 generates a
compare A signal when the T16A_TCx register value matches the T16A_CCAx register.
notes: • T16A2 must be placed into comparator mode to set half clock mode, as it is effective only
when PWM waveform is generated.
Be sure to set T16A2 to normal clock mode under a condition shown below.
(1) When T16A2 is placed into capture mode
(2) When TOUTAMD/T16A_CCCTLx register is set to 0x2 or 0x3
(3) When TOUTBMD/T16A_CCCTLx register is set to 0x2 or 0x3
• The dual-edge counter value cannot be read.
• Do not use the compare A interrupt in half clock mode.
D[5:4] CCaBCnT[1:0]: Counter Select Bits
Selects a counter to be connected to the comparator/capture block of each channel in multi-comparator/
capture mode (MULTIMD/T16A_CLK0 register = 1).
When using the T16A2 module in normal channel mode (T16A2MULTIMD = 0), be sure to connect
the counter of the same channel to each comparator/capture block.
D3 CBuFen: Compare Buffer enable Bit
Enables or disables writing to the compare buffer.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting CBUFEN to 1 enables the compare buffer. The compare A and B signals will be generated by
comparing the counter values with the compare A and B buffer values instead of the compare A and B
register values. The compare A and B register values written via software are loaded to the compare A
and B buffers when the compare B signal is generated.
13-14
name Function
reserved
hCM
Half clock mode enable
Counter select
[1:0]
CBuFen Compare buffer enable
TRMD
Count mode select
PReSeT Counter reset
PRun
Counter run/stop control
Table 13. 8.4 Counter Selection
CCaBCnT[1:0]
0x3, 0x2
0x1
0x0
Seiko epson Corporation
Setting init. R/W
–
1 Enable 0 Disable
CCABCNT[1:0] Counter Ch. 0x0 R/W
0x3, 0x2 reserved
0x1 Ch.1
0x0 Ch.0
1 Enable 0 Disable
1 One-shot 0 Repeat
1 Reset 0 Ignored
1 Run 0 Stop
Counter channel
Reserved
Ch.1 (Counter 1)
Ch.0 (Counter 0)
(Default: 0x0)
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 W 0 when being read.
0 R/W