Epson S1C17624 Technical Manual page 94

9 i/O PORTS (P)
9.4 Pull-up Control
The I/O port contains a pull-up resistor that can be enabled or disabled individually for each bit using PxPUy/Px_
PU register. Setting PxPUy to 1 (default) enables the pull-up resistor and pulls up the port pin in input mode. It will
not be pulled up if set to 0. The PxPUy setting is ignored and not pulled up in output mode, regardless of how the
PxIENy is set.
I/O ports that are not used should be set with pull-up enabled.
This pull-up setting is also enabled for ports for which the peripheral module function has been selected.
A delay will occur in the waveform rising edge depending on time constants such as pull-up resistance and pin load
capacitance if the port pin is switched from Low level to High level through the internal pull-up resistor. An ap-
propriate wait time must be set for the I/O port loading. The wait time set should be a value not less than that calcu-
lated from the following equation.
× (C
Wait time = R
IN IN
R : pull-up resistance maximum value, C
IN
9.5 input interface level
Some I/O ports allow software to select the input interface level from two types: CMOS Schmitt level and CMOS
level.
I/O port
CMOS Schmitt level
(PxSMy = 1)
P00–P07 (Selectable)
P10–P15 (Selectable)
P16–P17
P20–P27
P30–P37
P40
DSIO (P41)
DST2 (P42)
*
DCLK (P43)
P44–P47 (Selectable)
P50–P52 (Selectable)
P53–P56
* DCLK (P43) is an output-only port.
(Selectable) The input interface can be selected using the PxSMy bit.
(Fixed) The input interface level is fixed at CMOS Schmitt level.
The input interface level for the I/O ports listed with "
ing PxSMy/Px_SM register. Setting PxSMy to 1 (default) selects CMOS Schmitt level; setting to 0 selects CMOS
level.
The input interface level for the I/O ports listed with "
switched to CMOS level. In the S1C17624/622/604, the PxSMy bits for these ports are read-only bits (always read as
1) and cannot be altered. In the S1C17602/621, both 1 and 0 can be written to and read from these bits. However, the
input interface level cannot be switched.
9.6 P0 and P1 Port Chattering Filter Function
The P0 and P1 ports include a chattering filter circuit for key entry that can be disabled or enabled with a check
time specified individually for the four Px[3:0] and Px[7:4] ports using PxCF1[2:0]/Px_CHAT register and
PxCF2[2:0]/Px_CHAT register, respectively.
9-4
+ load capacitance on board) × 1.6 [s]
IN
Table 9. 5.1 Input Interface Level
S1C17624/622
CMOS level
(PxSMy = 0)
(Selectable)
(Selectable)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
–
(Selectable)
(Selectable)
(Fixed)
Seiko epson Corporation
: pin capacitance maximum value
CMOS Schmitt level
(PxSMy = 1)
(Selectable)
(Selectable)
×
(Fixed)
×
(Fixed)
×
(Fixed)
×
(Fixed)
×
(Fixed)
×
(Fixed)
–
×
(Selectable)" can be selected individually for each bit us-
(Fixed)" is fixed at CMOS Schmitt level and cannot be
S1C17624/604/622/602/621 TeChniCal Manual
S1C17604/602/621
CMOS level
(PxSMy = 0)
(Selectable)
(Selectable)
×
×
×
×
×
×
– –