Epson S1C17624 Technical Manual page 177

16 Stopwatch Timer (SWT)
16.1 SWT Module Overview
The S1C17624/604/622/602/621 includes a 1/100-second stopwatch timer module (SWT) that uses the OSC1 oscil-
lator as its clock source. This timer can be used to implement a software stopwatch function.
The features of the SWT module are listed below.
• Two 4-bit BCD counters (approximately 1/100 and 1/10-second counters)
• Approximately 100 Hz, approximately 10 Hz, and 1 Hz interrupts can be generated.
Figure 16.1.1 shows the SWT configuration.
CLG
OSC1
256 Hz
oscillator/divider
Run/Stop control
To ITC
The SWT module consists of two 4-bit BCD counters (1/100 and 1/10 second) that use the 256 Hz signal divided
from the OSC1 clock as the input clock and allows count data to be read out by software.
The SWT module can also generate interrupts using the 100 Hz (approximately 100 Hz), 10 Hz (approximately 10
Hz), and 1 Hz signals.
16.2 Operation Clock
The SWT module uses the 256 Hz clock output by the CLG module as the operation clock. The CLG module
generates this operation clock by dividing the OSC1 clock into 1/128, resulting in a frequency of 256 Hz when
the OSC1 clock frequency is 32.768 kHz. The frequency described in this chapter will vary accordingly for other
OSC1 clock frequencies. The CLG module does not include a 256 Hz clock output control bit. The 256 Hz clock is
normally supplied to the SWT module when the OSC1 oscillation is on.
For detailed information on OSC1 oscillator control, see the "Clock Generator (CLG)" chapter.
note: The OSC1 oscillator must be turned on before the SWT module can operate.
16.3 BCD Counters
The SWT module consists of 1/100-second and 1/10-second 4-bit BCD counters.
The 1/100-second and 1/10-second counter values can be read from BCD100[3:0]/SWT_BCNT register and
BCD10[3:0]/SWT_BCNT register, respectively.
Count-up Pattern
A feedback divider is used to generate 100 Hz, 10 Hz, and 1 Hz signals from the 256 Hz clock. The counter
count-up pattern varies as shown in Figure 16.3.1.
S1C17624/604/622/602/621 TeChniCal Manual
Count
SWTRST
Reset
control circuit
SWTRUN
SIE100
Interrupt
SIE10
enable
Interrupt
SIE1
control circuit
Interrupt request
Figure 16. 1.1 SWT Configuration
Seiko epson Corporation
16 STOPWaTCh TiMeR (SWT)
Feedback 1/100 s 4-bit
divider BCD counter
Approx. 100 Hz
Approx. 10 Hz
1 Hz
Stopwatch timer
1/10 s 4-bit
BCD counter
16-1