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28
Multiplier/Divider (COPRO)
28.1
Overview
The S1C17624/604/622/602/621 has an embedded coprocessor that provides multiplier/divider functions.
The following shows the features of the multiplier/divider:
• Multiplication:
• Multiplication and accumulation (MAC): Supports signed MAC operations with overflow detection function.
• Division:
S1C17 Core
28.2
Operation Mode and Output Mode
The Multiplier/divider operates according to the operation mode specified by the application program. As listed in
Table 28.2.1, the multiplier/divider supports nine operations.
The multiplication, division and MAC results are 32-bit data, therefore, the S1C17 Core cannot read them in one
access cycle. The output mode is provided to specify the high-order 16 bits or low-order 16 bits of the operation
results to be read from the multiplier/divider.
The operation and output modes can be specified with a 7-bit data by writing it to the mode setting register in the
multiplier/divider. Use a "ld.cw" instruction for this writing.
ld.cw
%rd,%rs
ld.cw
%rd,imm7
6
Output mode setting value
S1C17624/604/622/602/621 TeChniCal Manual
Supports signed/unsigned multiplications.
(16 bits × 16 bits = 32 bits)
Can be executed in 1 cycle.
(16 bits × 16 bits + 32 bits = 32 bits)
Can be executed in 1 cycle.
Supports signed/unsigned divisions.
(16 bits ÷ 16 bits = 16 bits with 16-bit residue)
Can be executed in 17 to 20 cycles.
Argument 2
Argument 1
Arithmetic unit
Operation result
register
Selector
Coprocessor
output
Flag output
Figure 28.
1.1 Multiplier/Divider Block Diagram
%rs[6:0] is written to the mode setting register. (%rd: not used)
imm7[6:0] is written to the mode setting register. (%rd: not used)
4
3
Figure 28.
2.1 Mode Setting Register
Seiko epson Corporation
28 MulTiPlieR/DiViDeR (COPRO)
Mode setting
Operation
result
Operation mode setting value
0
28-1
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