Epson S1C17624 Technical Manual page 197

18 uaRT
D4 Tien: Transmit Buffer empty interrupt enable Bit
Enables interrupt requests to the ITC caused when transmission data in the transmit data buffer is sent
to the shift register (i.e. when data transmission begins).
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to write data to the transmit data buffer using interrupts.
D[3:2] Reserved
D1 RBFi: Receive Buffer Full interrupt Condition Setup Bit
Sets the quantity of data in the receive data buffer to generate a receive buffer full interrupt.
1 (R/W): 2 bytes
0 (R/W): 1 byte (default)
If receive buffer full interrupts are enabled (RIEN = 1), the UART outputs an interrupt request to the
ITC when the quantity of received data specified by RBFI is loaded into the receive data buffer.
If RBFI is 0, an interrupt request is output as soon as one received data is loaded into the receive data
buffer (when RDRY/UART_STx register is set to 1). If RBFI is 1, an interrupt request is output as soon
as two received data are loaded into the receive data buffer (when RD2B/UART_STx register is set to 1).
D0 RXen: uaRT enable Bit
Enables data transfer by the UART.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set RXEN to 1 before starting UART transfers. Setting RXEN to 0 disables data transfers. The data
being transferred cannot be guaranteed if RXEN is set to 0 while data is being sent or received. Before
setting RXEN to 0, check the data transfer status with software in consideration of the communication
procedure. The data transmit status can be checked using the TRBS flag.
Disabling transfers by writing 0 to RXEN also clears transmit data buffer.
uaRT Ch.x expansion Registers (uaRT_eXPx)
Register name address Bit
uaRT Ch.x 0x4105 D7
expansion 0x4125
D6–4 iRClK[2:0] IrDA receive detection clock
Register
(8 bits)
(uaRT_eXPx)
D3–1 –
D0
D7 Reserved
D[6:4] iRClK[2:0]: irDa Receive Detection Clock Division Ratio Select Bits
Selects a PCLK division ratio to generate the IrDA input pulse detection clock.
Table 18.
18-12
name Function
– reserved
division ratio select
reserved
iRMD IrDA mode select
9.2 IrDA Receive Detection Clock (PCLK Division Ratio) Selection
iRClK[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
Setting init. R/W
–
IRCLK[2:0] Division ratio 0x0 R/W Source clock = PCLK
0x7 1/128
0x6 1/64
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
–
1 On 0 Off
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
– – 0 when being read.
– – 0 when being read.
0 R/W