Epson S1C17624 Technical Manual page 240

Cmos 16-bit single chip microcontroller
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D[11:8]
lCClK[3:0]: length Counter Clock Division Ratio Select Bits
Selects a data length counter clock (PCLK division ratio).
Table 22.
lCClK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
note: The clock should be set only while the REMC module is stopped (REMEN = 0).
D[7:2]
Reserved
D1
ReMMD: ReMC Mode Select Bit
Selects the transfer direction.
1 (R/W): Reception
0 (R/W): Transmission (default)
D0
ReMen: ReMC enable Bit
Enables or disables data transfer by the REMC module.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting REMEN to 1 starts transmission or receiving in accordance with REMMD settings.
Setting REMEN to 0 disables REMC module operations.
ReMC Carrier length Setup Register (ReMC_CaR)
Register name address
Bit
ReMC Carrier
0x5342
D15–14 –
length Setup
(16 bits)
D13–8 ReMCl[5:0] Carrier L length setup
Register
D7–6 –
(ReMC_CaR)
D5–0 ReMCh[5:0] Carrier H length setup
D[15:14] Reserved
D[13:8]
ReMCl[5:0]: Carrier l length Setup Bits
Sets the carrier signal L section length. (Default: 0x0)
Specify a value corresponding to the number of carrier generation clock cycles selected by CGCLK[3:0]/
REMC_CFG register + 1. Calculate carrier L section length as follows:
Carrier L section length = —————— [s]
REMCL: REMCL[5:0] setting
cg_clk:
The H section length is specified by REMCH[5:0]. The carrier signal is generated from these settings as
shown in Figure 22.7.1.
D[7:6]
Reserved
D[5:0]
ReMCh[5:0]: Carrier h length Setup Bits
Sets the carrier signal H section length. (Default: 0x0)
Specify a value corresponding to the number of carrier generation clock cycles selected by CGCLK[3:0]/
REMC_CFG register + 1. Calculate carrier H section length as follows:
S1C17624/604/622/602/621 TeChniCal Manual
7.3 Data Length Counter Clock (PCLK Division Ratio) Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
name
Function
reserved
reserved
REMCL + 1
cg_clk
Carrier generation clock frequency
Seiko epson Corporation
22 iR ReMOTe COnTROlleR (ReMC)
lCClK[3:0]
Division ratio
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Setting
init. R/W
0x0 to 0x3f
0x0 R/W
0x0 to 0x3f
0x0 R/W
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)
Remarks
0 when being read.
0 when being read.
22-7

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