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0x4100–0x4105
Register name address
Bit
uaRT Ch.0
0x4100
D7
Status Register
(8 bits)
D6
(uaRT_ST0)
D5
D4
D3
D2
D1
D0
uaRT Ch.0
0x4101
D7–0 TXD[7:0]
Transmit Data
(8 bits)
Register
(uaRT_TXD0)
uaRT Ch.0
0x4102
D7–0 RXD[7:0]
Receive Data
(8 bits)
Register
(uaRT_RXD0)
uaRT Ch.0
0x4103
D7–5 –
Mode Register
(8 bits)
D4
(uaRT_MOD0)
D3
D2
D1
D0
uaRT Ch.0
0x4104
D7
Control Register
(8 bits)
D6
(uaRT_CTl0)
D5
D4
D3–2 –
D1
D0
uaRT Ch.0
0x4105
D7
expansion
(8 bits)
D6–4 iRClK[2:0] IrDA receive detection clock
Register
(uaRT_eXP0)
D3–1 –
D0
0x4120–0x4125
Register name address
Bit
uaRT Ch.1
0x4120
D7
Status Register
(8 bits)
D6
(uaRT_ST1)
D5
D4
D3
D2
D1
D0
uaRT Ch.1
0x4121
D7–0 TXD[7:0]
Transmit Data
(8 bits)
Register
(uaRT_TXD1)
uaRT Ch.1
0x4122
D7–0 RXD[7:0]
Receive Data
(8 bits)
Register
(uaRT_RXD1)
uaRT Ch.1
0x4123
D7–5 –
Mode Register
(8 bits)
D4
(uaRT_MOD1)
D3
D2
D1
D0
S1C17624/604/622/602/621 TeChniCal Manual
name
Function
–
reserved
FeR
Framing error flag
PeR
Parity error flag
OeR
Overrun error flag
RD2B
Second byte receive flag
TRBS
Transmit busy flag
RDRY
Receive data ready flag
TDBe
Transmit data buffer empty flag
Transmit data
TXD7(6) = MSB
TXD0 = LSB
Receive data in the receive data
buffer
RXD7(6) = MSB
RXD0 = LSB
reserved
Chln
Character length select
PRen
Parity enable
PMD
Parity mode select
STPB
Stop bit select
SSCK
Input clock select
–
reserved
Reien
Receive error int. enable
Rien
Receive buffer full int. enable
Tien
Transmit buffer empty int. enable
reserved
RBFi
Receive buffer full int. condition setup 1 2 bytes
RXen
UART enable
–
reserved
division ratio select
reserved
iRMD
IrDA mode select
name
Function
–
reserved
FeR
Framing error flag
PeR
Parity error flag
OeR
Overrun error flag
RD2B
Second byte receive flag
TRBS
Transmit busy flag
RDRY
Receive data ready flag
TDBe
Transmit data buffer empty flag
Transmit data
TXD7(6) = MSB
TXD0 = LSB
Receive data in the receive data
buffer
RXD7(6) = MSB
RXD0 = LSB
reserved
Chln
Character length select
PRen
Parity enable
PMD
Parity mode select
STPB
Stop bit select
SSCK
Input clock select
Seiko epson Corporation
aPPenDiX a liST OF i/O ReGiSTeRS
uaRT (with irDa) Ch.0
Setting
init. R/W
–
1 Error
0 Normal
1 Error
0 Normal
1 Error
0 Normal
1 Ready
0 Empty
1 Busy
0 Idle
1 Ready
0 Empty
1 Empty
0 Not empty
0x0 to 0xff (0x7f)
0x0 R/W
0x0 to 0xff (0x7f)
0x0
–
1 8 bits
0 7 bits
1 With parity
0 No parity
1 Odd
0 Even
1 2 bits
0 1 bit
1 External
0 Internal
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
–
0 1 byte
1 Enable
0 Disable
–
IRCLK[2:0]
Division ratio
0x0 R/W Source clock = PCLK
1/128
0x7
0x6
1/64
0x5
1/32
0x4
1/16
0x3
1/8
0x2
1/4
0x1
1/2
0x0
1/1
–
1 On
0 Off
uaRT (with irDa) Ch.1
Setting
init. R/W
–
1 Error
0 Normal
1 Error
0 Normal
1 Error
0 Normal
1 Ready
0 Empty
1 Busy
0 Idle
1 Ready
0 Empty
1 Empty
0 Not empty
0x0 to 0xff (0x7f)
0x0 R/W
0x0 to 0xff (0x7f)
0x0
–
1 8 bits
0 7 bits
1 With parity
0 No parity
1 Odd
0 Even
1 2 bits
0 1 bit
1 External
0 Internal
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
0
R
0
R
Shift register status
0
R
1
R
R
Older data in the buf-
fer is read out first.
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
–
–
0 when being read.
0
R/W
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
0
R
0
R
Shift register status
0
R
1
R
R
Older data in the buf-
fer is read out first.
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
aP-a-5
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