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SPICLKx (CPOL = 1, CPHA = 1)
SPICLKx (CPOL = 1, CPHA = 0)
SPICLKx (CPOL = 0, CPHA = 1)
SPICLKx (CPOL = 0, CPHA = 0)
SDIx/SDOx
Fetching received data
into shift register
MSB first/lSB first settings
Use MLSB/SPI_CTLx register to select whether the data MSB or LSB is input/output first.
MSB first is selected when MLSB is 0 (default); LSB first is selected when MLSB is 1.
19.5
Data Transfer Control
Make the following settings before starting data transfers.
(1) Select the SPI clock source. (See Section 19.3.)
(2) Select master mode or slave mode. (See Section 19.4.)
(3) Set clock conditions. (See Section 19.4.)
(4) Set the interrupt conditions to use SPI interrupts. (See Section 19.6.)
note: Make sure the SPI is halted (SPEN/SPI_CTLx register = 0) before setting the above conditions.
enabling data transfers
Set SPEN/SPI_CTLx register to 1 to enable SPI operations. This enables SPI transfers and clock input/output.
note: Do not set SPEN to 0 when the SPI module is transferring data.
Data transmission control
To start data transmission, write the transmit data to SPTDB[7:0]/SPI_TXDx register.
The data is written to the transmit data buffer, and the SPI module starts sending data. The buffer data is sent
to the transmit shift register. In master mode, the module starts clock output from the SPICLKx pin. In slave
mode, the module awaits clock input from the SPICLKx pin. The data in the shift register is shifted in sequence
at the clock rising or falling edge, as determined by CPHA/SPI_CTLx register and CPOL/SPI_CTLx register (see
Figure 19.4.1) and sent from the SDOx pin.
The SPI module includes two status flags for transfer control: SPTBE/SPI_STx register and SPBSY/SPI_STx
register.
The SPTBE flag indicates the transmit data buffer status. This flag switches to 0 when the application program
writes data to the SPI_TXDx register (transmit data buffer) and reverts to 1 when the buffer data is sent to the
transmit shift register. An interrupt can be generated when this flag is set to 1 (see Section 19.6). Subsequent
data is sent after confirming that the transmit data buffer is empty either by using this interrupt or by inspecting
the SPTBE flag. The transmit data buffer size is 1 byte, but a shift register is provided separately to allow data
to be written while the previous data is being sent. Always confirm that the transmit data buffer is empty before
writing transmit data. Writing data while the SPTBE flag is 0 will overwrite earlier transmit data inside the
transmit data buffer.
In master mode, the SPBSY flag indicates the shift register status. This flag switches to 1 when transmit data is
loaded from the transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag to
check whether the SPI module is operating or at standby.
In slave mode, SPBSY flag indicates the SPI slave selection signal (#SPISSx pin) status. The flag is set to 1
when the SPI module is selected as a slave module and is set to 0 when the module is not selected.
S1C17624/604/622/602/621 TeChniCal Manual
D7 (MSB)
Figure 19.
4.1 Clock and Data Transfer Timing
Seiko epson Corporation
19 SPi
D0 (LSB)
19-3
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