Epson S1C17624 Technical Manual page 172

15 Clock Timer (CT)
15.1 CT Module Overview
The S1C17624/604/622/602/621 includes a clock timer module (CT) that uses the OSC1 oscillator as its clock
source. This timer can be used for generating cyclic interrupts to implement a software clock function.
The features of the CT module are listed below.
• 8-bit binary counter (128 Hz to 1 Hz)
• 32 Hz, 8 Hz, 2 Hz, and 1 Hz interrupts can be generated.
Figure 15.1.1 shows the CT configuration.
CLG
OSC1
256 Hz
oscillator/divider
Run/Stop control
To ITC
The CT module consists of an 8-bit binary counter that uses the 256 Hz signal divided from the OSC1 clock as the
input clock and allows data for each bit (128 Hz to 1 Hz) to be read out by software. The clock timer can also gen-
erate interrupts using the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. This clock timer is normally used for various timing
functions, such as a clock.
15.2 Operation Clock
The CT module uses the 256 Hz clock output by the CLG module as the operation clock. The CLG module gener-
ates this operation clock by dividing the OSC1 clock into 1/128, resulting in a frequency of 256 Hz when the OSC1
clock frequency is 32.768 kHz. The frequency described in this chapter will vary accordingly for other OSC1 clock
frequencies.
The CLG module does not include a 256 Hz clock output control bit. The 256 Hz clock is normally supplied to the
clock timer when the OSC1 oscillation is on.
For detailed information on OSC1 oscillator control, see the "Clock Generator (CLG)" chapter.
note: The OSC1 oscillator must be turned on before the CT module can operate.
15.3 Timer Reset
Reset the timer by writing 1 to CTRST/CT_CTL register. This clears the counter to 0.
Apart from this operation, the counter is also cleared by an initial reset.
15.4 Timer Run/STOP Control
Make the following settings before starting CT.
(1) If using interrupts, set the interrupt level and enable interrupts for the clock timer. See Section 15.5.
(2) Reset the timer. See Section 15.3.
The clock timer includes CTRUN/CT_CTL register for Run/Stop control.
S1C17624/604/622/602/621 TeChniCal Manual
CTRST
Timer reset
control circuit
CTRUN
CTIE32
CTIE8
Interrupt
enable
CTIE2 Interrupt
CTIE1 control circuit
Clock timer interrupt request
Figure 15. 1.1 CT Configuration
Seiko epson Corporation
D0 D1 D2
Count
128 64 32
Hz Hz Hz
15 ClOCK TiMeR (CT)
Clock timer
CT_CNT
D3 D4 D5 D6 D7
16 8 4 2 1
Hz Hz Hz Hz Hz
15-1