Table of Contents
Advertisement
5 iniTial ReSeT
5.1.3
Resetting by the Watchdog Timer
The S1C17624/604/622/602/621 has a built-in watchdog timer to detect runaway of the CPU. The watchdog timer
overflows if it is not reset with software (due to CPU runaway) in four-second cycles. The overflow signal can gen-
erate either NMI or reset. Write 1 to the WDTMD/WDT_ST register to generate reset (NMI occurs when WDTMD
= 0).
For details of the watchdog timer, see the "Watchdog Timer (WDT)" chapter.
notes: • When using the reset function of the watchdog timer, program the watchdog timer so that it
will be reset within four-second cycles to avoid occurrence of an unnecessary reset.
• The reset function of the watchdog timer cannot be used for power-on reset as it must be en-
abled with software.
5.2
initial Reset Sequence
Even if the #RESET pin input negates the reset signal after power is turned on, the CPU cannot boot up until the
oscillation stabilization waiting time (64 / IOSC clock frequency) has elapsed.
Figure 5.2.1 shows the operating sequence following cancellation of initial reset.
The CPU starts operating in synchronization with the IOSC (internal oscillator) clock after reset state is canceled.
note: The oscillation stabilization time described in this section does not include oscillation start time.
Therefore the time interval until the CPU starts executing instructions after power is turned on or
SLEEP mode is canceled may be longer than that indicated in the figure below.
IOSC clock
#RESET
Internal reset
Internal data request
Internal data address
Figure 5.
5.3
initial Settings after an initial Reset
The CPU internal registers are initialized as follows at initial reset.
R0–R7: 0x0
PSR:
0x0 (interrupt level = 0, interrupt disabled)
SP:
0x0
PC:
Reset vector stored at the beginning of the vector table is loaded by the reset handling.
The internal RAM and display memory should be initialized with software as they are not initialized at initial reset.
The internal peripheral modules are initialized to the default values (except some undefined registers). Change the
settings with software if necessary. For the default values set at initial reset, see the list of I/O registers in Appendix
or descriptions for each peripheral module.
5-2
Reset canceled
Oscillation stabilization
2.1 Operation Sequence Following Cancellation of Initial Reset
Seiko epson Corporation
Internal reset canceled
waiting time
S1C17624/604/622/602/621 TeChniCal Manual
Boot vector
Booting
Advertisement
Table of Contents
