Epson S1C17624 Technical Manual page 231

2
21 i C SlaVe (i2CS)
If BFREQ_EN/I2CS_CTL register has been set to 1 (bus free request enabled), a low pulse longer than
five peripheral module clock (PCLK) cycles input to the #BFR pin sets BFREQ to 1 and the bus free
request is accepted. When a bus free request is accepted, the I2CS module initializes the I
cation process and puts the SDA1 and SCL1 pins into high-impedance. The control registers will not be
initialized in this process.
At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN/
I2CS_ICTL register. This interrupt can be used to perform an error handling.
After BFREQ is set to 1, it is reset to 0 by writing 1.
If BFREQ_EN is set to 0, low pulse inputs to the #BFR pin are ignored and BFREQ is not set to 1.
D3 DMS: Output Data Mismatch Bit
Represents the results of comparison between output data and SDA line status.
1 (R/W): Error has been occurred
0 (R/W): Error has not been occurred (default)
The I 2 C bus SDA line status during data transmission is input in the module and is compared with the
output data. The comparison results are set to DMS. DMS is set to 0 when data is output correctly. If
the SDA line status is different from the output data, DMS is set to 1. This may be caused by a low pull-
up resistor value or another device that is controlling the SDA line. At the same time, an interrupt signal
is output to the ITC if the interrupt is enabled with BSTAT_IEN/I2CS_ICTL register. This interrupt can
be used to perform an error handling. After DMS is set to 1, it is reset to 0 by writing 1.
note: When the master device of the I
ing this IC, starts communication with another slave device, the I2CS module of this IC issues
NAK in response to the sent slave address. On the other hand, the selected slave device is-
sues ACK. Therefore, DMS may be set due to a difference between the output value of this IC
and the SDA line status. When SELECTED/I2CS_ASTAT register is set to 0, you can ignore
DMS without a problem even if it is set to 1 as there is a difference in the response code (ACK/
NAK) from the selected slave device.
When the I2CS module is placed into asynchronous address detection mode (ASDET_EN = 1),
a DMS does not occur as in the condition above.
D2 aSDeT: async. address Detection Status Bit
Indicates the asynchronous address detection status.
1 (R/W): Detected
0 (R/W): Not detected (default)
The I2CS module operation clock (PCLK) frequency must be set eight-times or higher than the transfer
rate during data transfer. However, the PCLK frequency can be lowered to reduce current consumption
if no other processing is required during standby for data transfer. The asynchronous address detection
function is provided to detect the I
1 if the slave address of the I2CS module is detected when the asynchronous address detection function
has been enabled by setting ASDET_EN/I2CS_CTL register.
The I2CS module returns a NAK to the I
same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN/I2CS_
ICTL register. Set the PCLK frequency to eight-times or higher than the transfer rate and reset ASDET_
EN to 0 in the interrupt handler routine. Data transfer will be able to resume normally after the master
retries transmission. After ASDET is set to 1, it is reset to 0 by writing 1.
D1 Da_naK: naK Receive Status Bit
Indicates the acknowledge bit returned from the master.
1 (R/W): NAK
0 (R/W): ACK (default)
DA_NAK is set to 0 when an ACK is returned from the master after an eight-bit data has been sent.
This indicates that the master could receive data. If DA_NAK is 1, it indicates that the master could not
receive data or the master terminates data reception. At the same time DA_NAK is set to 1, an interrupt
signal is output to the ITC if the interrupt is enabled with BSTAT_IEN/I2CS_ICTL register. This inter-
rupt can be used to perform an error handling. After DA_NAK is set to 1, it is reset to 0 by writing 1.
21-14
2 C bus, which has multiple slave devices connected includ-
2 C slave address sent from the master in this status. ASDET is set to
2
C master to request for resending the slave address. At the
Seiko epson Corporation
S1C17624/604/622/602/621 TeChniCal Manual
2 C communi-