Epson S1C17624 Technical Manual page 239

22 iR ReMOTe COnTROlleR (ReMC)
Falling edge interrupt
Generated when the REMI pin input signal changes from High to Low, this interrupt cause sets the interrupt
flag REMFIF/REMC_INT register to 1 within the REMC.
By running the data length counter between this interrupt and a rising edge interrupt when data is being re-
ceived, the received data pulse width can be calculated from that count value.
To use this interrupt, set REMFIE/REMC_INT register to 1. If REMFIE is set to 0 (default), the interrupt re-
quest attributable to this cause will not be sent to the ITC.
When REMFIF is set to 1, REMC outputs an interrupt request to the ITC. An interrupt will be generated if the
ITC and S1C17 Core interrupt conditions are met.
REMFIF should be inspected in the REMC interrupt handler routine to determine whether the REMC interrupt
is attributable to input signal falling edge.
The interrupt cause should be cleared in the interrupt handler routine by resetting (writing 1 to) REMFIF.
For more information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
22.7 Control Register Details
address
0x5340 REMC_CFG REMC Configuration Register
0x5342 REMC_CAR REMC Carrier Length Setup Register
0x5344 REMC_LCNT REMC Length Counter Register
0x5346 REMC_INT REMC Interrupt Control Register
The REMC registers are described in detail below. These are 16-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
ReMC Configuration Register (ReMC_CFG)
Register name address Bit
ReMC 0x5340 D15–12 CGClK[3:0] Carrier generator clock division
Configuration
(16 bits)
Register
(ReMC_CFG)
D11–8 lCClK[3:0] Length counter clock division ratio
D7–2 –
D1
D0
D[15:12] CGClK[3:0]: Carrier Generator Clock Division Ratio Select Bits
Selects a carrier generation clock (PCLK division ratio).
Table 22.
CGClK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
22-6
Table 22. 7.1 List of REMC Registers
Register name
name Function
ratio select
select
reserved
ReMMD
REMC mode select
ReMen
REMC enable
7.2 Carrier Generation Clock (PCLK Division Ratio) Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
Seiko epson Corporation
Function
Controls the clock and data transfer.
Sets the carrier H/L section lengths.
Sets the transmit/receive data length.
Controls interrupts.
Setting
CGCLK[3:0]
Division ratio
LCCLK[3:0]
0xf reserved
0xe 1/16384
0xd 1/8192
0xc 1/4096
0xb 1/2048
0xa 1/1024
0x9 1/512
0x8 1/256
0x7 1/128
0x6 1/64
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
–
1 Receive 0 Transmit
1 Enable 0 Disable
CGClK[3:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
S1C17624/604/622/602/621 TeChniCal Manual
init. R/W Remarks
0x0 R/W Source clock = PCLK
0x0 R/W
– – 0 when being read.
0 R/W
0 R/W
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)