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12 16-BiT PWM TiMeR (T16e)
Count clock
Counter value
T16E_CAx register
T16E_CBx register
Compare A signal
Compare B signal
TOUTx output (INVOUT = 0)
TOUTx output (INVOUT = 1)
The output duty can be adjusted in fine mode in count clock half-cycle steps. Note that a pulse will be output
with one count clock cycle width when compare data A = 0 (same as for default). The maximum value for com-
pare data B in fine mode is 2
Fine mode is set using SELFM/T16E_CTLx register.
Writing 1 to SELFM sets T16E into fine mode. Fine mode is disabled after an initial reset.
Precautions
(1) Compare data should be set with A ≥ 0 and B ≥ 1 when using the timer output. The minimum settings are A
= 0 and B = 1, and the timer output cycle is half the input clock.
(2) Setting compare data with A > B (A > B × 2 for fine mode) generates a compare B match signal only. It
does not generate a compare A match signal. In this case, the TOUTx output is fixed at low (high when IN-
VOUT = 1), and the TOUTNx output is fixed at high (low when INVOUT = 1).
(3) When fine mode is used, set compare data with B < A / 2 + 0x8000.
(4) Be sure to set T16EDF[3:0]/T16E_DFx register to 0x0 (PCLK•1/1) when using fine mode.
12.8
T16e interrupts
The T16E module can generate the following two kinds of interrupts:
• Compare A interrupt
• Compare B interrupt
A T16E timer channel outputs a single interrupt signal shared by the above interrupt causes to the interrupt control-
ler (ITC). Read the interrupt flags in the T16E module to identify the interrupt cause that has been occurred.
Compare a interrupt
This interrupt request is generated when the counter matches the compare data A register value during count-
ing. It sets the interrupt flag CAIF/T16E_IFLGx register within the T16E module to 1.
To use this interrupt, set CAIE/T16E_IMSKx register to 1. If CAIE is set to 0 (default), CAIF will not be set to 1,
and the interrupt request for this cause will not be sent to the ITC.
Compare B interrupt
This interrupt request is generated when the counter matches the compare data B register value during count-
ing. It sets the interrupt flag CBIF/T16E_IFLGx register within the T16E module to 1.
To use this interrupt, set CBIE/T16E_IMSKx register to 1. If CBIE is set to 0 (default), CBIF will not be set to 1,
and the interrupt request for this cause will not be sent to the ITC.
If the interrupt flag is set to 1 when the interrupt has been enabled, the T16E module outputs an interrupt request to
the ITC. An interrupt is generated if the ITC and S1C17 core interrupt conditions are satisfied.
For more information on interrupt control registers and the operation when an interrupt occurs, see the "Interrupt
Controller (ITC)" chapter.
notes: • Reset the interrupt flag before enabling interrupts with the interrupt enable bit to prevent oc-
currence of unwanted interrupt. The interrupt flag is reset by writing 1.
• After an interrupt occurs, the interrupt flag in the T16E module must be reset in the interrupt
handler routine.
12-6
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1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3
2
3
Figure 12.
7.3 Fine Mode Clock Output
- 1 = 32,767, and the compare data A range will be 0 to (2 × compare data B - 1).
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S1C17624/604/622/602/621 TeChniCal Manual
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