Epson S1C17624 Technical Manual page 292

Cmos 16-bit single chip microcontroller
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SVD Detection Result Register (SVD_RSlT)
Register name address
Bit
SVD Detection
0x5102
D7–1 –
Result Register
(8 bits)
D0
(SVD_RSlT)
D[7:1]
Reserved
D0
SVDDT: SVD Detection Result Bit
Indicates the power supply voltage detection results.
1 (R):
Power supply voltage (V
0 (R):
Power supply voltage (V
The SVD circuit compares the power supply voltage (V
CMP register while SVDEN/SVD_EN register = 1. The current power supply voltage status can be
checked by reading SVDDT.
SVD interrupt Mask Register (SVD_iMSK)
Register name address
Bit
SVD interrupt
0x5103
D7–1 –
Mask Register
(8 bits)
D0
(SVD_iMSK)
D[7:1]
Reserved
D0
SVDie: SVD interrupt enable Bit
Enables or disables interrupts when a power supply voltage drop is detected.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting SVDIE to 1 enables SVD interrupt requests to the ITC; setting to 0 disables interrupts.
SVD interrupt Flag Register (SVD_iFlG)
Register name address
Bit
SVD interrupt
0x5104
D7–1 –
Flag Register
(8 bits)
D0
(SVD_iFlG)
D[7:1]
Reserved
D0
SVDiF: SVD interrupt Flag Bit
Indicates the power supply voltage drop detection interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
SVDIF is set to 1 when a power supply voltage drop is detected. SVDIF is reset to 0 by writing 1.
S1C17624/604/622/602/621 TeChniCal Manual
name
Function
reserved
SVDDT
SVD detection result
) < comparison voltage
DD
) ≥ comparison voltage
DD
name
Function
reserved
SVDie
SVD interrupt enable
name
Function
reserved
SVDiF
SVD interrupt flag
Seiko epson Corporation
26 SuPPlY VOlTaGe DeTeCTOR (SVD)
Setting
init. R/W
1 Low
0 Normal
) against the voltage set in SVDC[3:0]/SVD_
DD
Setting
init. R/W
1 Enable
0 Disable
Setting
init. R/W
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
Remarks
0 when being read.
×
R
Remarks
0 when being read.
0
R/W
Remarks
0 when being read.
0
R/W Reset by writing 1.
26-5

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