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16 STOPWaTCh TiMeR (SWT)
256 Hz
3
256
Approximate 100 Hz
(Feedback divider output)
0
1/100-second counter
Approximate 10 Hz
(1/100-second counter output)
26
256
Approximate 10 Hz
(1/100-second counter output)
0
1/10-second counter
1 Hz
(1/10-second counter output)
The feedback divider generates an approximate 100 Hz signal at 2/256-second and 3/256-second intervals from
the 256 Hz signal supplied from the CLG module.
The 1/100-second counter counts the approximate 100 Hz signal output by the feedback divider and gener-
ates an approximate 10 Hz signal at 25/256-second and 26/256-second intervals. Count-up will be pseudo
1/100-second counting at 2/256-second and 3/256-second intervals.
The 1/10-second counter counts the approximate 10 Hz signal generated by the 1/100-second counter at a ra-
tio of 4:6, and generates a 1 Hz signal. Count-up will be pseudo 1/10-second counting at 25/256-second and
26/256-second intervals.
16.4
Timer Reset
Reset the SWT module by writing 1 to SWTRST/SWT_CTL register. This clears the counter to 0.
Apart from this operation, the counter is also cleared by initial reset.
16.5
Timer Run/STOP Control
Make the following settings before starting SWT.
(1) If using interrupts, set the interrupt level and enable interrupts for the SWT module. See Section 16.6.
(2) Reset the timer. See Section 16.4.
The SWT module includes SWTRUN/SWT_CTL register for Run/Stop control.
The timer starts operating when 1 is written to SWTRUN. Writing 0 to SWTRUN disables clock input and stops
the operation. This control does not affect the counter (SWT_BCNT register) data. The counter data is retained
even when the count is halted, allowing resumption of the count from that data. If 1 is written to both SWTRUN
and SWTRST simultaneously, the timer starts counting after resetting.
A cause of interrupt occurs during counting at the 100 Hz (approximate 100 Hz), 10 Hz (approximate 10 Hz), and 1
Hz signal falling edges. If interrupts are enabled, an interrupt request is sent to the interrupt controller (ITC).
16-2
1/100-second counter count-up pattern 1
2
3
2
3
2
3
256
256
256
256
256
256
1
2
3
4
5
6
25
s
256
26
25
25
s
s
s
256
256
256
1
2
Figure 16.
3.1 SWT Count-Up Patterns
Seiko epson Corporation
1/100-second counter count-up pattern 2
2
3
2
3
3
256
256
256
256
256
7
8
9
0
1
1/10-second counter count-up pattern
26
26
s
s
s
256
256
3
4
5
26
× 6 + 25
× 4 = 1 s
256
256
S1C17624/604/622/602/621 TeChniCal Manual
3
2
3
2
3
2
256
256
256
256
256
256
2
3
4
5
6
7
26
s
256
25
25
26
s
s
s
256
256
256
6
7
8
3
2
256
256
8
9
26
s
256
9
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