Epson S1C17624 Technical Manual page 121

Cmos 16-bit single chip microcontroller
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D[7:0]
TR[7:0]: Reload Data Bits
Sets the counter initial value. (Default: 0x0)
The reload data set in this register is preset to the counter when the timer is reset or the counter under-
flows. If the timer is started after resetting, it counts down from the reload value (initial value). This
means that the reload value and the input clock frequency determine the time elapsed from the point at
which the timer starts until the underflow occurs (or between underflows). The time determined is used
to obtain the desired wait time, the intervals between periodic interrupts, and the programmable serial
interface transfer clock.
T8F Ch.x Counter Data Registers (T8F_TCx)
Register name address
Bit
T8F Ch.x
0x4204
D15–8 –
Counter Data
0x4284
D7–0 TC[7:0]
Register
(16 bits)
(T8F_TCx)
D[15:8]
Reserved
D[7:0]
TC[7:0]: Counter Data Bits
The counter data can be read out. (Default: 0xff)
This register is read-only and cannot be written to.
T8F Ch.x Control Registers (T8F_CTlx)
Register name address
Bit
T8F Ch.x
0x4206
D15–12 –
Control Register
0x4286
D11–8 TFMD[3:0]
(T8F_CTlx)
(16 bits)
D7–5 –
D4
D3–2 –
D1
D0
D[15:12] Reserved
D[11:8]
TFMD[3:0]: Fine Mode Setup Bits
Corrects the transfer rate error. (Default: 0x0)
TFMD[3:0] specifies the delay pattern to be inserted into a 16 underflow period. Inserting one delay
extends the output clock cycle by one count clock cycle. This setting delays the interrupt timing in the
same way.
TFMD[3:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
S1C17624/604/622/602/621 TeChniCal Manual
name
Function
reserved
Counter data
TC7 = MSB
TC0 = LSB
name
Function
reserved
Fine mode setup
reserved
TRMD
Count mode select
reserved
PReSeR
Timer reset
PRun
Timer run/stop control
Table 10.
10.3 Delay Patterns Specified by TFMD[3:0]
1
2
3
4
5
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Seiko epson Corporation
10 Fine MODe 8-BiT TiMeRS (T8F)
Setting
0x0 to 0xff
Setting
0x0 to 0xf
1 One shot
0 Repeat
1 Reset
0 Ignored
1 Run
0 Stop
underflow number
6
7
8
9
10
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D: Indicates the insertion of a delay cycle.
init. R/W
Remarks
0 when being read.
0xff
R
init. R/W
Remarks
0 when being read.
0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
0 when being read.
0
R/W
0 when being read.
0
W
0
R/W
11
12
13
14
15
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
16
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
10-7

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