The Receive Data Buffer - Epson S1C17624 Technical Manual

19 SPi
D[15:10] Reserved
D9 MClK: SPi Clock Source Select Bit
Selects the SPI clock source.
1 (R/W): 16-bit timer Ch.1
0 (R/W): PCLK/4 (default)
D8 MlSB: lSB/MSB First Mode Select Bit
Selects whether data is transferred with MSB first or LSB first.
1 (R/W): LSB first
0 (R/W): MSB first (default)
D[7:6] Reserved
D5 SPRie: Receive Data Buffer Full interrupt enable Bit
Enables or disables SPI receive data buffer full interrupts.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting SPRIE to 1 enables the output of SPI interrupt requests to the ITC due to a receive data buffer
full. These interrupt requests are generated when the data received in the shift register is transferred to
the receive data buffer (when reception is completed).
SPI interrupts are not generated by receive data buffer full if SPRIE is set to 0.
D4 SPTie: Transmit Data Buffer empty interrupt enable Bit
Enables or disables SPI transmit data buffer empty interrupts.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting SPTIE to 1 enables the output of SPI interrupt requests to the ITC due to a transmit data buffer
empty. These interrupt requests are generated when the data written to the transmit data buffer is trans-
ferred to the shift register (when transmission starts).
SPI interrupts are not generated by transmit data buffer empty if SPTIE is set to 0.
note: In the S1C17602/621, the transmit buffer empty interrupt can only be used in master mode.
In the S1C17624/604/622, the transmit buffer empty interrupt can be used in both master and
slave modes.
D3 CPha: Clock Phase Select Bit
Selects the SPI clock phase. (Default: 0)
Set the data transfer timing together with CPOL. (See Figure 19.7.1.)
D2 CPOl: Clock Polarity Select Bit
Selects the SPI clock polarity.
1 (R/W): Active Low
0 (R/W): Active High (default)
Set the data transfer timing together with CPHA. (See Figure 19.7.1.)
SPICLKx (CPOL = 1, CPHA = 1)
SPICLKx (CPOL = 1, CPHA = 0)
SPICLKx (CPOL = 0, CPHA = 1)
SPICLKx (CPOL = 0, CPHA = 0)
SDIx/SDOx
Fetching received data
into shift register
19-8
D7 (MSB)
Figure 19. 7.1 Clock and Data Transfer Timing
Seiko epson Corporation
S1C17624/604/622/602/621 TeChniCal Manual
D0 (LSB)