Epson S1C17624 Technical Manual page 61

7 ClOCK GeneRaTOR (ClG)
7.2 ClG input/Output Pins
Table 7.2.1 lists the input/output pins for the CLG module.
Pin name i/O
OSC1 I
OSC2 O
OSC3 I
OSC4 O
FOUT1 O
FOUTH O
The CLG output pins (FOUT1, FOUTH) are shared with I/O ports and are initially set as general purpose I/O port
pins. The pin functions must be switched using the port function select bits to use the general purpose I/O port pins
as the CLG output pins. For detailed information on pin function switching, see the "I/O Ports (P)" chapter.
7.3 Oscillators
The CLG module contains three internal oscillator circuits (IOSC, OSC3, and OSC1). The IOSC and OSC3 oscilla-
tors generate the main clock for high-speed operation of the S1C17 Core and peripheral circuits. The OSC1 oscilla-
tor generates a sub-clock for timers and low-power operations. The IOSC clock is selected as the system clock after
an initial reset. Oscillator on/off switching and system clock selection (from IOSC, OSC3 and OSC1) are controlled
with software.
7.3.1 iOSC Oscillator
The IOSC oscillator initiates high-speed oscillation without external components. It initiates oscillation when pow-
er is turned on. The S1C17 Core and peripheral circuits operate with this oscillation clock after an initial reset.
SLEEP/NORMAL
iOSC oscillation on/off
The IOSC oscillator stops oscillating when IOSCEN/OSC_CTL register is set to 0 and starts oscillating when
set to 1. The IOSC oscillator stops oscillating in SLEEP mode.
After an initial reset, IOSCEN is set to 1, and the IOSC oscillator goes on. Since the IOSC clock is used as the
system clock, the S1C17 Core starts operating using the IOSC clock.
Stabilization wait time at start of iOSC oscillation
The IOSC oscillator circuit includes an oscillation stabilization wait circuit to prevent malfunctions due to un-
stable clock operations at the start of IOSC oscillation—e.g., when the IOSC oscillator is turned on with soft-
ware. Figure 7.3.1.2 shows the relationship between the oscillation start time and the oscillation stabilization
wait time.
7-2
Table 7. 2.1 List of CLG Pins
Qty
1 OSC1 oscillator input pin
Connect a crystal resonator (32.768 kHz) and a gate capacitor.
1 OSC1 oscillator output pin
Connect a crystal resonator (32.768 kHz).
1 OSC3 oscillator input pin
Connect a crystal or ceramic resonator (max. 8.2 MHz), a feedback resistor, and
a gate capacitor. Or Input an external clock used as the OSC3 clock.
1 OSC3 oscillator output pin
Connect a crystal or ceramic resonator (max. 8.2 MHz), a feedback resistor, and
a drain capacitor.
1 FOUT1 clock output pin
Outputs the OSC1 clock.
1 FOUTH clock output pin
Outputs a divided IOSC/OSC3 clock.
Clock
generator
IOSCEN
Figure 7. 3.1.1 IOSC Oscillator Circuit
Seiko epson Corporation
Function
Oscillation stabilization
wait circuit
IOSCWT[1:0]
S1C17624/604/622/602/621 TeChniCal Manual
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IOSC