Epson S1C17624 Technical Manual page 245

23 lCD DRiVeR (lCD)
23.3 lCD Clock
Figure 23.3.1 shows the LCD clock supply system.
LCKDV[2:0]
Divider
HSCLK
(1/32–1/512)
OSC1
23.3.1 lCD Operating Clock (lClK)
Clock source selection
Use LCKSRC/OSC_LCLK register to select the clock source from HSCLK (IOSC or OSC3) and OSC1. Set-
ting LCKSRC to 1 (default) selects OSC1 and setting it to 0 selects HSCLK.
Clock division ratio selection
When the clock source is OSC1
No division ratio needs to be selected when OSC1 is selected for the clock source. The OSC1 clock (typ.
32.768 kHz) is directly used as LCLK.
When the clock source is hSClK
When HSCLK is selected for the clock source, use LCKDV[2:0]/OSC_LCLK register to select the division
ratio.
Clock enable
The LCLK supply is enabled with LCKEN/OSC_LCLK register. The LCKEN default setting is 0, which stops
the clock. Setting LCKEN to 1 feeds the clock generated as above to the LCD driver. If no LCD display is re-
quired, stop the clock to reduce current consumption.
If LCLK is not supplied, the LCD cannot display. However, the LCD driver control registers and display mem-
ory can be accessed even if LCLK is stopped.
note: Be sure to set LCKEN to 0 before selecting a clock division ratio.
23.3.2 Frame Signal
The LCD driver generates the frame signal by dividing LCLK. The clock division ratio can be set using FRM-
CNT[1:0]/LCD_CCTL register. Figures 23.4.2.1 to 23.4.2.5 show one cycle of the frame frequency as "1 frame."
Tables 23.3.2.1 and 23.3.2.2 list the frame frequencies that can be programmed.
23-2
LCKEN
LCLK
LCKSRC
Figure 23. 3.1 LCD Clock System
Table 23. 3.1.1 HSCLK Division Ratio Selection
lCKDV[2:0]
0x7–0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
Divider
Synchronous clock
(1/16)
LFRO output
Divider Frame signal
FRMCNT[1:0]
Division ratio
Reserved
1/512
1/256
1/128
1/64
1/32
(Default: 0x0)
S1C17624/604/622/602/621 TeChniCal Manual