Epson S1C17624 Technical Manual page 246

When the clock source is OSC1
Table 23.
Drive duty
(lDuTY[2:0] setting)
1/8 duty (0x4)
1/4 duty (0x3)
1/3 duty (0x2)
1/2 duty (0x1)
Static (0x0)
When the clock source is hSClK
Drive duty
(lDuTY[2:0] setting)
1/8 duty (0x4)
1/4 duty (0x3)
1/3 duty (0x2)
1/2 duty (0x1)
Static (0x0)
* Default setting, f
HSCLK
The frame signal generated can be output to an external device via the LFRO pin. To output the frame signal, set
LFROUT/LCD_CCTL register to 1. However, the output pin must be switched for LFRO output using the port
function select bit, as the pin is configured for an I/O port by default. For detailed information on pin function
switching, see the "I/O Ports (P)" chapter.
23.4 Drive Duty Control
23.4.1 Drive Duty Switching
Drive duty can be set to 1/8, 1/4, 1/3, 1/2 or static drive using LDUTY[2:0]/LCD_CCTL register. Tables 23.4.1.1
and 23.4.1.2 show the correspondence between LDUTY[2:0] settings, drive duty, and maximum number of display
segments.
S1C17624/622
lDuTY[2:0]
0x7–0x5
0x4
0x3
0x2
0x1
0x0
The COM4/SEG55 to COM7/SEG52 pins are configured to COM pins when 1/8 duty is selected or SEG pins
when other duty is selected.
S1C17624/604/622/602/621 TeChniCal Manual
3.2.1 Frame Frequency Settings (when OSC1 = 32.768 kHz)
FRMCnT[1:0] setting (lClK division ratio)
0x0
128 Hz (1/256) 64 Hz (1/512) *
128 Hz (1/256) 64 Hz (1/512)
130.04 Hz (1/252) 65.02 Hz (1/504)
128 Hz (1/256) 64 Hz (1/512)
128 Hz (1/256) 64 Hz (1/512)
Table 23. 3.2.2 Frame Frequency Settings
0x0
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
256
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
256
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
252
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
256
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
256
: HSCLK (IOSC or OSC3) clock frequency, LCKDV: HSCLK division ratio (1/32 to 1/512)
Table 23. 4.1.1 Drive Duty Settings (S1C17624/622)
Duty Valid COM pins
Reserved
1/8 COM0 to COM7
1/4 COM0 to COM3
1/3 COM0 to COM2
1/2 COM0 to COM1
Static
Seiko epson Corporation
0x1 0x2
48.19 Hz (1/680)
48.19 Hz (1/680)
48.12 Hz (1/681)
48.19 Hz (1/680)
48.19 Hz (1/680)
FRMCnT[1:0] setting
0x1 0x2
× LCKDV * × LCKDV
f
HSCLK
––––––––––––––
512 680
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
512 680
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
504 681
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
512 680
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
512 680
Valid SeG pins
–
SEG0 to SEG51
SEG0 to SEG55
SEG0 to SEG55
SEG0 to SEG55
COM0 SEG0 to SEG55
23 lCD DRiVeR (lCD)
0x3
32 Hz (1/1024)
32 Hz (1/1024)
32.5 Hz (1/1008)
32 Hz (1/1024)
32 Hz (1/1024)
* Default setting
0x3
× LCKDV
f
HSCLK
––––––––––––––
1024
× LCKDV
f
HSCLK
––––––––––––––
1024
× LCKDV
f
HSCLK
––––––––––––––
1008
× LCKDV
f
HSCLK
––––––––––––––
1024
× LCKDV
f
HSCLK
––––––––––––––
1024
Max. number of
display segments
– –
416 segments
224 segments
168 segments
112 segments
56 segments
(Default: 0x4)
23-3