Epson S1C17624 Technical Manual page 111

P4[3:0] Port Function Select Register (P40_43PMuX)
Register name address Bit
P4[3:0] Port 0x52a8 D7–6 P43MuX[1:0] P43 port function select
Function Select
(8 bits)
Register
(P40_43PMuX)
D5–4 P42MuX[1:0] P42 port function select
D3–2 P41MuX[1:0] P41 port function select
D1–0 P40MuX[1:0] P40 port function select
The P40 to P43 port pins are shared with the peripheral module pins. This register is used to select how the pins are
used.
D[7:6] P43MuX[1:0]: P43 Port Function Select Bits
0x3 (R/W): Reserved
0x2 (R/W): Reserved
0x1 (R/W): P43
0x0 (R/W): DCLK (DBG) (default)
P43 is an output-only port and no external signal cannot be input.
To use P43 as a general-purpose output port, make the following settings:
1. Set P4OEN3/P4_OEN register to 1 (output).
2. Set P43MUX[1:0] to 0x1 (P43).
When the P43 output port is not used (or used as the DCLK port), make the following settings:
1. Set P43MUX[1:0] to 0x0 (DCLK).
2. Set P4OEN3 to 0 (input).
D[5:4] P42MuX[1:0]: P42 Port Function Select Bits
0x3 (R/W): Reserved
0x2 (R/W): Reserved
0x1 (R/W): P42
0x0 (R/W): DST2 (DBG) (default)
D[3:2] P41MuX[1:0]: P41 Port Function Select Bits
0x3 (R/W): Reserved
0x2 (R/W): Reserved
0x1 (R/W): P41
0x0 (R/W): DSIO (DBG) (default)
D[1:0] P40MuX[1:0]: P40 Port Function Select Bits
0x3 (R/W): Reserved
0x2 (R/W): Reserved
0x1 (R/W): FOUTH (CLG)
0x0 (R/W): P40 (default)
S1C17624/604/622/602/621 TeChniCal Manual
name Function
Seiko epson Corporation
Setting init. R/W
P43MUX[1:0] Function 0x0 R/W
0x3 reserved
0x2 reserved
0x1 P43
0x0 DCLK
P42MUX[1:0] Function 0x0 R/W
0x3 reserved
0x2 reserved
0x1 P42
0x0 DST2
P41MUX[1:0] Function 0x0 R/W
0x3 reserved
0x2 reserved
0x1 P41
0x0 DSIO
P40MUX[1:0] Function 0x0 R/W
0x3 reserved
0x2 reserved
0x1 FOUTH
0x0 P40
9 i/O PORTS (P)
Remarks
9-21