Epson S1C17624 Technical Manual page 191

18 uaRT
Framing error
A framing error occurs if the stop bit is received as 0 and the UART determines loss of sync. If the stop bit is
set to two bits, only the first bit is checked.
The framing error flag FER/UART_STx register is set to 1 if this error occurs. The received data is still trans-
ferred to the receive data buffer if this error occurs and the receiving operation continues, but the data cannot be
guaranteed, even if no framing error occurs for subsequent data receiving. The FER flag is reset to 0 by writing 1.
Overrun error
Even if the receive data buffer is full (two 8-bit data already received), the third data can be received in the shift
register. However, if the receive data buffer is not emptied (by reading out data received) by the time this data
has been received, the third data received in the shift register will not be sent to the buffer and generate an over-
run error. If an overrun error occurs, the overrun error flag OER/UART_STx register is set to 1. The receiving
operation continues even if this error occurs. The OER flag is reset to 0 by writing 1.
18.7 uaRT interrupts
The UART includes a function for generating the following three different types of interrupts.
• Transmit buffer empty interrupt
• Receive buffer full interrupt
• Receive error interrupt
Each UART channel outputs one interrupt signal shared by the three above interrupt causes to the interrupt control-
ler (ITC). Inspect the status flag and error flag to determine the interrupt cause occurred.
Transmit buffer empty interrupt
To use this interrupt, set TIEN/UART_CTLx register to 1. If TIEN is set to 1 while TDBE/UART_STx register
is 1 (transmit data buffer empty) or if TDBE is set to 1 (when the transmit data buffer becomes empty by load-
ing the transmit data written to it to the shift register) while TIEN is 1, an interrupt request is sent to the ITC.
An interrupt occurs if other interrupt conditions are met.
If TIEN is set to 0 (default), interrupt requests for this cause will not be sent to the ITC.
You can inspect the TDBE flag in the UART interrupt handler routine to determine whether the UART interrupt
is attributable to a transmit buffer empty. If TDBE is 1, the next transmit data can be written to the transmit data
buffer by the interrupt handler routine.
Receive buffer full interrupt
To use this interrupt, set RIEN/UART_CTLx register to 1. If RIEN is set to 0 (default), interrupt requests for
this cause will not be sent to the ITC.
If the specified volume of received data is loaded into the receive data buffer when a receive buffer full interrupt
is enabled (RIEN = 1), the UART outputs an interrupt request to the ITC. If RBFI/UART_CTLx register is 0,
an interrupt request is output as soon as one received data is loaded into the receive data buffer (when RDRY/
UART_STx register is set to 1). If RBFI is 1, an interrupt request is output as soon as two received data are
loaded into the receive data buffer (when RD2B/UART_STx register is set to 1).
An interrupt occurs if other interrupt conditions are met. You can inspect the RDRY and RD2B flags in the
UART interrupt handler routine to determine whether the UART interrupt is attributable to a receive buffer full.
If RDRY or RD2B is 1, the received data can be read from the receive data buffer by the interrupt handler rou-
tine.
Receive error interrupt
To use this interrupt, set REIEN/UART_CTLx register to 1. If REIEN is set to 0 (default), interrupt requests for
this cause will not be sent to the ITC.
The UART sets an error flag, PER, FER, or OER/UART_STx register to 1 if a parity error, framing error, or
overrun error is detected when receiving data. If receive error interrupts are enabled (REIEN = 1), an interrupt
request is sent simultaneously to the ITC.
18-6
Seiko epson Corporation
S1C17624/604/622/602/621 TeChniCal Manual