Epson S1C17624 Technical Manual page 120

10 Fine MODe 8-BiT TiMeRS (T8F)
10.10 Control Register Details
address
0x4200 T8F_CLK0 T8F Ch.0 Count Clock Select Register
0x4202 T8F_TR0 T8F Ch.0 Reload Data Register
0x4204 T8F_TC0 T8F Ch.0 Counter Data Register
0x4206 T8F_CTL0 T8F Ch.0 Control Register
0x4208 T8F_INT0 T8F Ch.0 Interrupt Control Register
0x4280 T8F_CLK1 T8F Ch.1 Count Clock Select Register
0x4282 T8F_TR1 T8F Ch.1 Reload Data Register
0x4284 T8F_TC1 T8F Ch.1 Counter Data Register
0x4286 T8F_CTL1 T8F Ch.1 Control Register
0x4288 T8F_INT1 T8F Ch.1 Interrupt Control Register
The T8F registers are described in detail below. These are 16-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
T8F Ch.x Count Clock Select Registers (T8F_ClKx)
Register name address Bit
T8F Ch.x Count 0x4200 D15–4 –
Clock Select 0x4280
D3–0 DF[3:0]
Register (16 bits)
(T8F_ClKx)
D[15:4] Reserved
D[3:0] DF[3:0]: Count Clock Division Ratio Select Bits
Selects a PCLK division ratio to generate the count clock.
DF[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
note: Make sure the counter is halted before setting the count clock.
T8F Ch.x Reload Data Registers (T8F_TRx)
Register name address Bit
T8F Ch.x 0x4202 D15–8 –
Reload Data 0x4282
D7–0 TR[7:0]
Register
(16 bits)
(T8F_TRx)
D[15:8] Reserved
10-6
Table 10. 10.1 List of T8F Registers
Register name
name Function
reserved
Count clock division ratio select
Table 10. 10.2 PCLK Division Ratio Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
name Function
reserved
Reload data
TR7 = MSB
TR0 = LSB
Seiko epson Corporation
Function
Selects a count clock.
Sets reload data.
Counter data
Sets the timer mode and starts/stops the timer.
Controls the interrupt.
Selects a count clock.
Sets reload data.
Counter data
Sets the timer mode and starts/stops the timer.
Controls the interrupt.
Setting
–
DF[3:0] Division ratio
0xf reserved
0xe 1/16384
0xd 1/8192
0xc 1/4096
0xb 1/2048
0xa 1/1024
0x9 1/512
0x8 1/256
0x7 1/128
0x6 1/64
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
DF[3:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Setting
–
0x0 to 0xff
S1C17624/604/622/602/621 TeChniCal Manual
init. R/W Remarks
– – 0 when being read.
0x0 R/W Source clock = PCLK
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)
init. R/W Remarks
– – 0 when being read.
0x0 R/W