Epson S1C17624 Technical Manual page 229

2
21 i C SlaVe (i2CS)
D5 naK_anS: naK answer Bit
Specifies the acknowledge bit to be sent after data reception.
1 (R/W): NAK
0 (R/W): ACK (default)
When an eight-bit data is received, the I2CS module sends back an ACK (SDA1 = low) or a NAK (SDA1
= Hi-Z). Either ACK or NAK should be specified using NAK_ANS within 7 cycles of the I
(SCL1 input clock) after RXRDY has been set to 1 by receiving the previous data.
D4 BFReQ_en: Bus Free Request enable Bit
Enables or disables I
1 (R/W): Enabled
0 (R/W): Disabled (default)
To accept I 2 C bus free requests, set BFREQ_EN to 1. When a bus free request is accepted, BFREQ/
I2CS_STAT register is set to 1. This initializes the I
SCL1 pins into high-impedance. The control registers will not be initialized in this process.
When BFREQ_EN is set to 0, low pulse inputs to the #BFR pin are ignored and BFREQ is not set to 1.
D3 ClKSTR_en: Clock Stretch On/Off Bit
Turns the clock stretch function on or off.
1 (R/W): On
0 (R/W): Off (default)
After data and ACK are transmitted or received, the slave device may issue a wait request to the master
device until it is ready to transmit/receive by pulling the I
ule supports this clock stretch function. The master device enters a standby state until the wait request is
canceled (the SCL line goes high). When using the clock stretch function, set CLKSTR_EN to 1 before
starting data communication.
D2 nF_en: noise Filter On/Off Bit
Turns the noise filter on or off.
1 (R/W): On
0 (R/W): Off (default)
The I2CS module contains a function to remove noise from the SDA1 and SCL1 input signals. This
function is enabled by setting NF_EN to 1.
D1 aSDeT_en: async. address Detection On/Off Bit
Turns the asynchronous address detection function on or off.
1 (R/W): On
0 (R/W): Off (default)
The I2CS module operation clock (PCLK) frequency must be set eight-times or higher than the transfer
rate during data transfer. However, the PCLK frequency can be lowered to reduce current consumption
if no other processing is required during standby for data transfer.
The asynchronous address detection function is provided to detect the I
master in this status. This function is enabled by setting ASDET_EN to 1. If the slave address sent from
the master has matched with one that has been set in this I2CS module when the asynchronous address
detection function has been enabled, the I2CS module generates a bus status interrupt and returns NAK
to the I 2 C master to request for resending the slave address. Set the PCLK frequency to eight-times or
higher than the transfer rate and reset ASDET_EN to 0 in the interrupt handler routine. Data transfer
will be able to resume normally after the master retries transmission. After the master generates a stop
condition to put the I
again to lower the operating speed.
notes: • When the asynchronous address detection function is enabled, the I
without passing through the noise filter. Therefore, the slave address may not be detected in
a high-noise environment.
21-12
2
C bus free requests by inputting a low pulse to the #BFR pin.
2
C bus into free status, the asynchronous address detection function can be enabled
Seiko epson Corporation
2
C communication process and puts the SDA1 and
2 C bus SCL line down to Low. The I2CS mod-
2 C slave address sent from the
2
S1C17624/604/622/602/621 TeChniCal Manual
2 C clock
C bus signals are input