Table of Contents
Advertisement
D[3:0]
WDTRun[3:0]: Watchdog Timer Run/Stop Control Bits
Controls WDT Run/Stop.
Values other than 0b1010 (R/W): Run
0b1010 (R/W):
note: WDT must also be reset to prevent generation of an unnecessary NMI or Reset before start-
ing WDT.
Watchdog Timer Status Register (WDT_ST)
Register name address
Bit
Watchdog
0x5041
D7–2 –
Timer Status
(8 bits)
Register
D1
(WDT_ST)
D0
D[7:2]
Reserved
D1
WDTMD: nMi/Reset Mode Select Bit
Selects NMI or reset generation on counter overflow.
1 (R/W): Reset
0 (R/W): NMI (default)
Setting this bit to 1 outputs a reset signal when the counter overflows. Setting to 0 outputs an NMI sig-
nal.
D0
WDTST: nMi Status Bit
Indicates a counter overflow and NMI occurrence.
1 (R):
NMI occurred (counter overflow)
0 (R):
NMI not occurred (default)
This bit confirms that WDT was the source of the NMI. The WDTST set to 1 is cleared to 0 by resetting
WDT.
This is also set by a counter overflow if reset output is selected, but is cleared by initial reset and cannot
be confirmed.
S1C17624/604/622/602/621 TeChniCal Manual
Stop (default)
name
Function
reserved
WDTMD
NMI/Reset mode select
WDTST
NMI status
Seiko epson Corporation
17 WaTChDOG TiMeR (WDT)
Setting
init. R/W
–
1 Reset
0 NMI
1 NMI occurred 0 Not occurred
Remarks
–
–
0 when being read.
0
R/W
0
R
17-3
Advertisement
Table of Contents
