Oracle SPARC M8 Service Manual page 107

Hide thumbs Also See for SPARC M8:
Table of Contents

Advertisement

DIMM Configuration
The SPARC M7 CMIOU DIMM locations and the buffer chip (BOB) and DDR channel (CH)
numbers are as follows:
Servicing DIMMs
107

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

Sparc m7

Table of Contents