Section References; Per-Box Performance Monitoring Capabilities - Intel Xeon E5-2600 Series Monitoring Manual

Events can be collected by reading a set of local counter registers. Each counter register is paired with
a dedicated control register used to specify what to count (i.e. through the event select/umask fields)
and how to count it. Some units provide the ability to specify additional information that can be used
to 'filter' the monitored events (e.g., C-box; see
(Cn_MSR_PMON_BOX_FILTER)").
Uncore performance monitors represent a per-socket resource that is not meant to be affected by
context switches and thread migration performed by the OS, it is recommended that the monitoring
software agent establish a fixed affinity binding to prevent cross-talk of event counts from different
uncore PMU.
The programming interface of the counter registers and control registers fall into two address spaces:
• Accessed by MSR are PMON registers within the Cbo units, PCU, and U-Box, see
• Access by PCI device configuration space are PMON registers within the HA, iMC, Intel® QPI,
R2PCIe and R3QPI units, see
Irrespective of the address-space difference and with only minor exceptions, the bit-granular layout of
the control registers to program event code, unit mask, start/stop, and signal filtering via threshold/
edge detect are the same.
The general performance monitoring capabilities of each box are outlined in the following table.
Table 1-1.

Per-Box Performance Monitoring Capabilities

Box
C-Box
HA
iMC
PCU
QPI
R2PCIe
R3QPI
U-Box
1.3

Section References

The following sections provide a breakdown of the performance monitoring capabilities for each box.
• Section 2.1, "Uncore Per-Socket Performance Monitoring Control"
• Section 2.2, "UBox Performance Monitoring"
• Section 2.3, "Caching Agent (Cbo) Performance Monitoring"
• Section 2.6, "Power Control (PCU) Performance Monitoring"
• Section 2.4, "Home Agent (HA) Performance Monitoring"
• Section 2.5, "Memory Controller (iMC) Performance Monitoring"
• Section 2.7, "Intel® QPI Link Layer Performance Monitoring"
• Section 2.9, "R3QPI Performance Monitoring"
• Section 2.8, "R2PCIe Performance Monitoring"
• Section 2.10, "Packet Matching Reference"
10
Section 2.3.3.3, "CBo Filter Register
Table 1-3.
# Counters/
# Boxes
Box
8 4
1 4
1 4 (+1)
(4 channels) (per channel)
1 4 (+2)
1 4
(2 ports) (per port)
1 4
1 3
(2 links)
1 2 (+1)
# Queue Bus Packet Match/
Enabled Lock? Mask Filters?
1 N
4 Y
4 N
4 N
4 N
1 N
1 N
0 N/A
Reference Number: 327043-001
Introduction
Table 1-2.
Bit Width
Y 44
Y 48
N 48
N 48
Y? 48
N 44
N 44
N 44