Clock Generation - Xilinx ZCU102 User Manual

Clock Generation

The ZCU102 board provides fixed and variable clock sources for the XCZU9EG MPSoC.
Table 3-12 lists the source devices for each clock.
Table 3-12: ZCU102 Board Clock Sources
Clock Name
Fixed Frequency Clocks
PS_REF_CLK
CLK_74_25
CLK_125
GTR_REF_CLK_PCIE
PCIE_SLOT_CLK
GTR_REF_CLK_SATA
GTR_REF_CLK_USB3
GTR_REF_CLK_DP
Programmable Frequency Clocks
USER_SI570
USER_MGT_SI570
USER_MGT_SMA
HDMI_SI5324_OUT
SFP_SI5328_OUT
Table 3-13 lists the source devices for each clock.
Table 3-13: Clock Connections, Source to XCZU9EG MPSoC
Clock Source
Ref. Des. and Schematic Net Name
Pin
U69.59 PS_REF_CLK
U69.45 CLK_125_P
U69.44 CLK_125_N
U69.51 CLK_74_25_P
U69.50 CLK_74_25_N
U69.38 PCIE_SLOT_CLK_P
U69.37 PCIE_SLOT_CLK_N
U69.42 GTR_REF_CLK_PCIE_P
U69.41 GTR_REF_CLK_PCIE_N
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Frequency
33.33 MHz
74.25 MHz
125 MHz
100 MHz
100 MHz
125 MHz
24 MHz
27 MHz
300 MHz (Default) U42 SI570 I2C PROG. OSC.
156.2 MHz (Default) U56 SI570 I2C PROG. OSC.
J79 (P)/J80 (N) SMA CONN.
User-Provided Source
Variable U108 Clock Recovery
Variable U20 Clock Recovery
I/O Standard
(1)
LVDS_25
LVDS_25
LVDS_25
LVDS_25
N/A
N/A
(2)
(2)
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Chapter 3: Board Component Descriptions
Clock Source
U69 SI5341B Clock Generator
FPGA (U1) Pin
U24
G21
F21
AK15
AK14
(PCIE CONNECTOR) P1.A13
(PCIE CONNECTOR) P1.A14
AA27
AA28
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