Xilinx ZCU102 User Manual page 121

set_property PACKAGE_PIN AH9
set_property IOSTANDARD
set_property PACKAGE_PINAP2
set_property IOSTANDARD SSTL12_DCI
#QSPI
#QSPI_LWR U119 and UPR U120 are connected to PS MIO Bank 500
#Other net PACKAGE_PIN AF16 - MIO0_QSPI_LWR_CLK
#Other net PACKAGE_PIN AJ16 - MIO1_QSPI_LWR_DQ1
#Other net PACKAGE_PIN AD16 - MIO2_QSPI_LWR_DQ2
#Other net PACKAGE_PIN AG16 - MIO3_QSPI_LWR_DQ3
#Other net PACKAGE_PIN AH16 - MIO4_QSPI_LWR_DQ0
#Other net PACKAGE_PIN AM15 - MIO5_QSPI_LWR_CS_B Bank 500
#Other net PACKAGE_PIN AD17 - MIO7_QSPI_UPR_CS_B Bank 500
#Other net PACKAGE_PIN AE17 - MIO8_QSPI_UPR_DQ0
#Other net PACKAGE_PIN AP15 - MIO9_QSPI_UPR_DQ1
#Other net PACKAGE_PIN AH17 - MIO10_QSPI_UPR_DQ2 Bank 500
#Other net PACKAGE_PIN AF17 - MIO11_QSPI_UPR_DQ3 Bank 500
#Other net PACKAGE_PIN AJ17 - MIO12_QSPI_UPR_CLK Bank 500
#FMC
#HPC0 J5
set_property PACKAGE_PIN AA6
set_property IOSTANDARD LVDS
set_property PACKAGE_PIN AA7
set_property IOSTANDARD LVDS
set_property PACKAGE_PIN R8
set_property IOSTANDARD LVDS
set_property PACKAGE_PIN T8
set_property IOSTANDARD LVDS
set_property PACKAGE_PIN G7
set_property PACKAGE_PIN G8
set_property PACKAGE_PIN L7
set_property PACKAGE_PIN L8
set_property PACKAGE_PIN G3
set_property PACKAGE_PIN G4
set_property PACKAGE_PIN H1
set_property PACKAGE_PIN H2
set_property PACKAGE_PIN H5
set_property PACKAGE_PIN H6
set_property PACKAGE_PIN J3
set_property PACKAGE_PIN J4
set_property PACKAGE_PIN F5
set_property PACKAGE_PIN F6
set_property PACKAGE_PIN F1
set_property PACKAGE_PIN F2
set_property PACKAGE_PIN K5
set_property PACKAGE_PIN K6
set_property PACKAGE_PIN K1
set_property PACKAGE_PIN K2
set_property PACKAGE_PIN M5
set_property PACKAGE_PIN M6
set_property PACKAGE_PIN L3
set_property PACKAGE_PIN L4
set_property PACKAGE_PIN P5
set_property PACKAGE_PIN P6
set_property PACKAGE_PIN P1
set_property PACKAGE_PIN P2
set_property PACKAGE_PIN R3
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Appendix B:
[gt_ports "DDR4_RESET_B_LS"]
LVCMOS18 [gt_ports "DDR4_RESET_B_LS"]
[get_ports "DDR4_CS_B"]
[get_ports "DDR4_CS_B"]
[get_ports "FMC_HPC0_CLK0_M2C_N"]
[get_ports "FMC_HPC0_CLK0_M2C_N"]
[get_ports "FMC_HPC0_CLK0_M2C_P"]
[get_ports "FMC_HPC0_CLK0_M2C_P"]
[get_ports "FMC_HPC0_CLK1_M2C_N"]
[get_ports "FMC_HPC0_CLK1_M2C_N"]
[get_ports "FMC_HPC0_CLK1_M2C_P"]
[get_ports "FMC_HPC0_CLK1_M2C_P"]
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"]
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"]
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"]
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"]
[get_ports "FMC_HPC0_DP0_C2M_N"]
[get_ports "FMC_HPC0_DP0_C2M_P"]
[get_ports "FMC_HPC0_DP0_M2C_N"]
[get_ports "FMC_HPC0_DP0_M2C_P"]
[get_ports "FMC_HPC0_DP1_C2M_N"]
[get_ports "FMC_HPC0_DP1_C2M_P"]
[get_ports "FMC_HPC0_DP1_M2C_N"]
[get_ports "FMC_HPC0_DP1_M2C_P"]
[get_ports "FMC_HPC0_DP2_C2M_N"]
[get_ports "FMC_HPC0_DP2_C2M_P"]
[get_ports "FMC_HPC0_DP2_M2C_N"]
[get_ports "FMC_HPC0_DP2_M2C_P"]
[get_ports "FMC_HPC0_DP3_C2M_N"]
[get_ports "FMC_HPC0_DP3_C2M_P"]
[get_ports "FMC_HPC0_DP3_M2C_N"]
[get_ports "FMC_HPC0_DP3_M2C_P"]
[get_ports "FMC_HPC0_DP4_C2M_N"]
[get_ports "FMC_HPC0_DP4_C2M_P"]
[get_ports "FMC_HPC0_DP4_M2C_N"]
[get_ports "FMC_HPC0_DP4_M2C_P"]
[get_ports "FMC_HPC0_DP5_C2M_N"]
[get_ports "FMC_HPC0_DP5_C2M_P"]
[get_ports "FMC_HPC0_DP5_M2C_N"]
[get_ports "FMC_HPC0_DP5_M2C_P"]
[get_ports "FMC_HPC0_DP6_C2M_N"]
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Master Constraints File Listing
Bank 500
Bank 500
Bank 500
Bank 500
Bank 500
Bank 500
Bank 500
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