Xilinx ZCU102 User Manual page 44

Table 3-13: Clock Connections, Source to XCZU9EG MPSoC (Cont'd)
Clock Source
Ref. Des. and Schematic Net Name
Pin
U69.35 GTR_REF_CLK_SATA_P
U69.34 GTR_REF_CLK_SATA_N
U69.31 GTR_REF_CLK_USB3_P
U69.30 GTR_REF_CLK_USB3_N
U69.24 GTR_REF_CLK_DP_P
U69.23 GTR_REF_CLK_DP_N
U42.4 USER_SI570_P
U42.5 USER_SI570_N
U56.4 USER_MGT_SI570_P
U56.5 USER_MGT_SI570_N
U51.11 USER_MGT_SI570_CLOCK1_P
U51.12 USER_MGT_SI570_CLOCK1_N
U51.13 USER_MGT_SI570_CLOCK2_P
U51.14 USER_MGT_SI570_CLOCK2_N
J79.1 USER_SMA_MGT_CLOCK_P
J80.1 USER_SMA_MGT_CLOCK_N
U108.28 HDMI_SI5324_OUT_P
U108.29 HDMI_SI5324_OUT_N
U20.28 SFP_SI5328_OUT_P
U20.29 SFP_SI5328_OUT_N
Notes:
1. U1 XCU9EG Bank 503 supports LVCMOS level inputs.
2. U1 MGT (I/O standards do not apply).
SI5341B 10 Independent Output Any-Frequency Clock Generator (PS
Reference Clock)
[Figure 2-1, callout 10]
• Clock generator: Silicon Labs SI5341B-B05071-GM
• Jitter: <100 fs RMS typical
• Differential and single-ended outputs
The SI5341B is a one-time programmable clock source. For more details refer to the SI5341B
data sheet [Ref 17]
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
I/O Standard
DIFF_SSTL12
DIFF_SSTL12
for more details. The clock circuit is shown in
www.xilinx.com
Chapter 3: Board Component Descriptions
FPGA (U1) Pin
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1-to-2 CLOCK BUFFER) U51.6
(2)
(1-to-2 CLOCK BUFFER) U51.7
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
W27
W28
U27
U28
U31
U32
AL8
AL7
L27
L28
C8
C7
N27
N28
R27
R28
B10
B9
Figure 3-8.
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