Xilinx ZCU102 User Manual page 65

16-bit color depth at 1080p (1920 x 1080 / 60 Hz). The SN65DP159RGZ device can
automatically configure itself as a re-driver at data rates <1 Gb/s, or as a re-timer at more
than this data rate. This feature can be turned off through I2C programming.
The HDMI video output block diagram is shown in
Figure 3-24. The connections between the codec and the XCZU9EG MPSoC are listed in
Table 3-29.
X-Ref Target - Figure 3-23
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Figure 3-23: HDMI Interface Block Diagram
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Chapter 3: Board Component Descriptions
Figure 3-23, the interface circuit in
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