Hdmi Clock Recovery - Xilinx ZCU102 User Manual

Table 3-29: HDMI Retimer U94 Connections to FPGA U1 (Cont'd)
XCZU9EG
Schematic Net Name
(U1) Pin
D15 HDMI_RX_CEC_SINK
HDMI_RX_SNK_SCL
E15
A15 HDMI_RX_SNK_SDA
A16 HDMI_TX_CEC
B16 HDMI_TX_HPD
HDMI_SI5324_LOL
H12
J12 HDMI_SI5324_RST
F11 HDMI_SI5324_INT_ALM
HDMI_REC_CLOCK_C_P
AG5
AG4 HDMI_REC_CLOCK_C_N
R27 HDMI_SI5324_OUT_C_P
R28 HDMI_SI5324_OUT_C_N
HDMI_RX0_C_P
T33
T34 HDMI_RX0_C_N
P33 HDMI_RX1_C_P
HDMI_RX1_C_N
P34
N31 HDMI_RX2_C_P
N32 HDMI_RX2_C_N
N27 HDMI_RX_CLK_C_P
HDMI_RX_CLK_C_N
N28
D14 HDMI_RX_PWR_DET
E14 HDMI_RX_HPD
Notes:
1. U1 MGT (I/O standards do not apply).
2. SN65DP159 (U94), M24C64-W (U109), SI5324C (U108).

HDMI Clock Recovery

[Figure 2-1, callout 40]
The ZCU102 board includes a Silicon Labs Si5324C jitter attenuator U70 (2 kHz - 945 MHz).
The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 66
(HDMI_REC_CLOCK_C_P, pin Y8 and HDMI_REC_CLOCK_C_N, pin Y7) for jitter attenuation.
The jitter attenuated clock (HDMI_SI5324_OUT_C_P (U108 pin 28), HDMI_SI5324_OUT_C_N
(U108 pin 29) is then routed as a reference clock to GTH Quad 128 inputs MGTREFCLK0P (U1
pin R27) and MGTREFCLK0N (U1 pin R28).
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Chapter 3:
I/O Standard
Pin No.
LVCMOS33 24
LVCMOS33 1
LVCMOS33 1
LVCMOS33 24
LVCMOS33 3
LVCMOS33 18
LVCMOS33 1
LVCMOS33 3
LVDS 16
LVDS 17
(1)
28
(1)
29
(1)
B7
(1)
B9
(1)
B4
(1)
B6
(1)
B1
(1)
B3
(1)
B10
(1)
B12
LVCMOS33 3
LVCMOS33 1
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Board Component Descriptions
Connected Component
Pin Name
CEC_A
TPD12S016RK
SCL_A
SDA_A
CEC_A
TPD12S016RK
HPD_A
LOL
RST_B
INT_C1B
CKIN1_P SI5324C (U108)
CKIN1_N
CKOUT1_P
CKOUT1_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
HDMI BOTTOM
PORT(P7)
TMDS_DATA2_P
TMDS_DATA2_N
TMDS_CLK_P
TMDS_CLK_N
D
G
Send Feedback
Device
(U110)
(U70)
Q46
Q41
67