Block Diagram - Xilinx ZCU102 User Manual

Block Diagram

The ZCU102 board block diagram is shown in
diagram reference the corresponding page number(s) of schematic 0381701.
X-Ref Target - Figure 1-1
SFP 2x2 Cage
Page 34
FMC HPC0
GT Interface
Pages 26-29
FMC HPC0
LA Bus
SFP Recovered
Pages 26-29
Clock
FMC HPC0
Page 34
LA Bus
HDMI Recovered
Pages 41-43
Clock
FMC HPC1
Pages 35-37
LA Bus
Pages 30-33
HDMI TX Clock
Pages 35-37
DDR4 Comp.
Memory
16-bit: 1 x 16-bit
MT40A256M16GE-075E
Pages 26-29
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Prototype Header
Display Port Aux
MSP430 GPIO IIC0
Connection
Pages 44, 56, 38
GTH230
GTH229
GTH228
66
XCZU9EGFFVB1156
HP
65
HP
64
HP
SI570
BPIO
Programmable
74.25MHz clk
Oscillator
Page 39
Page 40
GTR Muxes
JTAG CONN.
Page 45
Page 22
Figure 1-1: ZCU102 Evaluation Board Block Diagram
www.xilinx.com
Figure 1-1. Page numbers in the block
PMOD
SYSMON IIC
125MHz CLK
SFP Disables
Trace
MSP430/CP2108 UART
IIC1 Connection
HDMI control
Pages 54-55, 58
Pages 6, 34
PS
49
502
48 47
50
PS
501
PS
U1
503
67
(PS-Side
HP
0
CONFIG)
PS PWR
PS
PS
44 504
500
PS DDR
PS UART DDR4 72-bit
PS I2C S0DIMM
PS QSPI
Pages 42, 46, 57-58 Page 23
MECHANICALS
PS/PL/System
Clock devices
Pages 39-41
Page 87
Chapter 1: Introduction
SDIO
Ethernet
PMU, GPIO
USB
PS Display Port Aux
Pages 51-52
Pages 47, 44-45
FMC HPC1
GT Interface
GTH130
Pages 30-33
GTH129
HDMI
SMA
GTH128
Pages 35-37, 40
PS
MUX connections:
GTR505 PCIe / DisplayPort
USB3.0 / SATA
Pages 43-45, 48, 51
INIT, DONE LEDs
PROG. PB
PS POR, SRST PBs
Page 12
DDR4 DIMM
DECOUPLING
Page 24
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