Xilinx ZCU102 User Manual page 116

set_property PACKAGE_PIN AL7
set_property IOSTANDARD
set_property PACKAGE_PIN AL8
set_property IOSTANDARD
set_property PACKAGE_PIN R9
set_property IOSTANDARD
set_property PACKAGE_PIN R10
set_property IOSTANDARD
set_property PACKAGE_PIN AG4
set_property IOSTANDARD
set_property PACKAGE_PIN AG5
set_property IOSTANDARD
set_property PACKAGE_PIN AG6
set_property IOSTANDARD
set_property PACKAGE_PIN AF6
set_property IOSTANDARD
#For completeness, the MGT clocks are documented here:
#MGTH 128 HDMI I/F
set_property PACKAGE_PIN R27
set_property PACKAGE_PIN R28
set_property PACKAGE_PIN N27
set_property PACKAGE_PIN N28
#MGTH 129 HPC1_DP[4:7]
set_property PACKAGE_PIN L27
set_property PACKAGE_PIN L28
set_property PACKAGE_PIN J27
set_property PACKAGE_PIN J28
#MGTH 130 HPC1_DP[0:3]
set_property PACKAGE_PIN G27
set_property PACKAGE_PIN G28
set_property PACKAGE_PIN E27
set_property PACKAGE_PIN E28
# MGTH 228 HPC0_DP[4:6]
set_property PACKAGE_PIN L8
set_property PACKAGE_PIN L7
#MGTH 229 HPC0_DP[0:3]
set_property PACKAGE_PIN G8
set_property PACKAGE_PIN G7
#MGTH 230 SFP0 I/F
set_property PACKAGE_PIN C8
set_property PACKAGE_PIN C7
set_property PACKAGE_PIN B10
set_property PACKAGE_PIN B9
#GTR 505 FIXED CLOCKS SOURCED FROM U69 SI5341B
#Other net PACKAGE_PIN AA27 - GTR_REF_CLK_PCIE_C_P
#Other net PACKAGE_PIN AA28 - GTR_REF_CLK_PCIE_C_N
#Other net PACKAGE_PIN W27 - GTR_REF_CLK_SATA_C_P
#Other net PACKAGE_PIN W28 - GTR_REF_CLK_SATA_C_N
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Appendix B:
[get_ports "USER_SI570_N"]
DIFF_SSTL12 [get_ports "USER_SI570_N"]
[get_ports "USER_SI570_P"]
DIFF_SSTL12 [get_ports "USER_SI570_P"]
[get_ports "SFP_REC_CLOCK_C_N"]
LVDS [get_ports "SFP_REC_CLOCK_C_N"]
[get_ports "SFP_REC_CLOCK_C_P"]
LVDS [get_ports "SFP_REC_CLOCK_C_P"]
[get_ports "HDMI_REC_CLOCK_C_N"]
LVDS [get_ports "HDMI_REC_CLOCK_C_N"]
[get_ports "HDMI_REC_CLOCK_C_P"]
LVDS [get_ports "HDMI_REC_CLOCK_C_P"]
[get_ports "HDMI_TX_LVDS_OUT_N"]
LVDS [get_ports "HDMI_TX_LVDS_OUT_N"]
[get_ports "HDMI_TX_LVDS_OUT_P"]
LVDS [get_ports "HDMI_TX_LVDS_OUT_P"]
[get_ports "HDMI_SI5324_OUT_C_P"]
[get_ports "HDMI_SI5324_OUT_C_N"]
[get_ports "HDMI_RX_CLK_C_P"]
[get_ports "HDMI_RX_CLK_C_N"]
[get_ports "USER_MGT_SI570_CLOCK1_C_P"]
[get_ports "USER_MGT_SI570_CLOCK1_C_N"]
[get_ports "USER_SMA_MGT_CLOCK_C_P"]
[get_ports "USER_SMA_MGT_CLOCK_C_N"]
[get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"]
[get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"]
[get_ports "FMC_HPC1_GBTCLK1_M2C_C_P"]
[get_ports "FMC_HPC1_GBTCLK1_M2C_C_N"]
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"]
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"]
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"]
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"]
[get_ports "USER_MGT_SI570_CLOCK2_C_P"]
[get_ports "USER_MGT_SI570_CLOCK2_C_N"]
[get_ports "SFP_SI5328_OUT_C_P"]
[get_ports "SFP_SI5328_OUT_C_N"]
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