Xilinx ZCU102 User Manual page 81

X-Ref Target - Figure 3-35
FMC HPC_0
Eight (8) MGTs in a common FPGA column are provided by PL-side MGT banks 229 and 230.
Available MGT reference clocks include the FMC defined GBT clocks 0 and 1 for HPC_0, a
programmable Si570 clock, and a jitter attenuated recovered clock from a Si5328. The MGT
reference clocks are located in adjacent MGT banks, 228, 229, and 230.
FMC HPC_1
Eight (8) MGTs in a common FPGA column are provided by PL-side MGT banks 129 and 130.
Available MGT reference clocks include the FMC defined GBT clocks 0 and 1 for HPC_1, a
programmable Si570 clock, and a user provided SMA clock. The MGT reference clocks are
located in adjacent MGT banks, 128, 129, and 130.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Figure 3-35: GTH Bank Assignments
www.xilinx.com
Chapter 3: Board Component Descriptions
Send Feedback
81