Xilinx ZCU102 User Manual page 55

X-Ref Target - Figure 3-17
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Figure 3-17: I2C0 Bus Topology
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Chapter 3: Board Component Descriptions
VCCPSPLL_EN
MGTRAVCC_EN
MGTRAVTT_EN
VCCPSDDRPLL_EN
MI026_PMU_INPUT_LS
PL_PMBUS_ALERT
PS_PMBUS_ALERT
MAXIM_PMBUS_ALERT
PL_DDR4_VTERM_EN
PL_DDR4_VPP_2V5_EN
PS_DIMM_VDDQ_TO_PSVCCO_ON
PS_DIMM_SUSPEND_EN
PS_DDR4_VTERM_EN
PS_DDR4_VPP_2V5_EN
PS_GTR_LANE_SEL0
PS_GTR_LANE_SEL1
PS_GTR_LANE_SEL2
PS_GTR_LANE_SEL3
PCIE_CLK_DIR_SEL
IIC_MUX_RESET_B
GEM3_EXP_RESET_B
FMC_HPC0_PRSNT_M2C_B
FMC_HPC1_PRSNT_M2C_B
MAXIM_PMBUS_SDA/SCL
SYSMON_SDA/SCL
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