Sfp/Sfp+ Clock Recovery - Xilinx ZCU102 User Manual

Table 3-30: XCZU9EG U1 to P2 SFP+ Module Quad-Connector (Cont'd)
XCZU9EG
Schematic Net Name
(U1) Pin
A8 SFP3_TX_P
A7 SFP3_TX_N
A4 SFP3_RX_P
SFP3_RX_N
A3
C13 SFP3_TX_DISABLE
Notes:
1. SFPx_TX_DISABLE pins should implement the LVCMOS33 I/O standard.

SFP/SFP+ Clock Recovery

[Figure 2-1, callout 11]
The ZCU102 board includes a Silicon Labs Si5328B jitter attenuator U20 (8 kHz - 808 MHz).
The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 67
(SFP_REC_CLOCK_C_P, pin R10 and SFP_REC_CLOCK_C_N, pin R9) for jitter attenuation.
The jitter attenuated clock (SFP_SI5328_OUT_C_P (U20 pin 28), SFP_SI5328_OUT_C_N (U20
pin 29)) is then routed as a reference clock to GTH Quad 230 inputs MGTREFCLK1P (U1 pin
B10) and MGTREFCLK1N (U1 pin B9).
The primary purpose of this clock is to support synchronous protocols such as CPRI or
OBSAI to perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter
attenuated recovered clock to drive the reference clock inputs of a GTH transceiver. The
system controller configures the SI5328B in free-run mode (see
Controller, page
programming from the FPGA through the I2C bus.The jitter attenuated clock circuit is
shown in Figure
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
SFP+ Pin
Location Left Lower SFP3
(1)
105). Enabling the jitter attenuation feature requires additional user
3-28.
www.xilinx.com
Chapter 3:
SFP+ Pin Name
LL18 LL_TD_P
LL19 LL_TD_N
LL13 LL_RD_P
LL_RD_N
LL12
LL3 LL_ TX_DISABLE
Board Component Descriptions
TI MSP430 System
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