Xilinx ZCU102 User Manual page 132

set_property PACKAGE_PIN B10[get_ports "SFP_SI5328_OUT_C_P"]
set_property PACKAGE_PIN H10[get_ports "SFP_SI5328_INT_ALM"]
set_property IOSTANDARDLVCMOS33 [get_ports "SFP_SI5328_INT_ALM"]
#I2C BUS
#I2C0
set_property PACKAGE_PIN J10
set_property IOSTANDARD
set_property PACKAGE_PIN J11
set_property IOSTANDARD
#I2C1
set_property PACKAGE_PIN K20
set_property IOSTANDARD
set_property PACKAGE_PIN L20
set_property IOSTANDARD
#SYSMON I2C
set_property PACKAGE_PIN B14
set_property IOSTANDARD
set_property PACKAGE_PIN C14
set_property IOSTANDARD
#DISPLAY PORT
set_property PACKAGE_PIN F12
set_property IOSTANDARD
set_property PACKAGE_PIN G11
set_property IOSTANDARD
set_property PACKAGE_PIN H11
set_property IOSTANDARD
set_property PACKAGE_PIN D10
set_property IOSTANDARD
#USER MGT I/O
set_property PACKAGE_PIN M34
set_property PACKAGE_PIN M33
set_property PACKAGE_PIN M30
set_property PACKAGE_PIN M29
#USER MGT CLOCK
set_property PACKAGE_PIN J28
set_property PACKAGE_PIN J27
set_property PACKAGE_PIN L28
set_property PACKAGE_PIN L27
set_property PACKAGE_PIN C7
set_property PACKAGE_PIN C8
#UART
set_property PACKAGE_PIN E13
set_property IOSTANDARD
set_property PACKAGE_PIN F13
set_property IOSTANDARD
set_property PACKAGE_PIN D12
set_property IOSTANDARD
set_property PACKAGE_PIN E12
set_property IOSTANDARD
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Appendix B:
[get_ports "PL_I2C0_SCL_LS"]
LVCMOS33 [get_ports "PL_I2C0_SCL_LS"]
[get_ports "PL_I2C0_SDA_LS"]
LVCMOS33 [get_ports "PL_I2C0_SDA_LS"]
[get_ports "PL_I2C1_SCL_LS"]
LVCMOS33 [get_ports "PL_I2C1_SCL_LS"]
[get_ports "PL_I2C1_SDA_LS"]
LVCMOS33 [get_ports "PL_I2C1_SDA_LS"]
[get_ports "SYSMON_SDA"]
LVCMOS33 [get_ports "SYSMON_SDA"]
[get_ports "SYSMON_SCL"]
LVCMOS33 [get_ports "SYSMON_SCL"]
[get_ports "PL_DPAUX_IN"]
LVCMOS33 [get_ports "PL_DPAUX_IN"]
[get_ports "PL_DP_OE"]
LVCMOS33 [get_ports "PL_DP_OE"]
[get_ports "PL_DP_HPD"]
LVCMOS33 [get_ports "PL_DP_HPD"]
[get_ports "PL_DPAUX_OUT"]
LVCMOS33 [get_ports "PL_DPAUX_OUT"]
[get_ports "SMA_MGT_RX_C_N"]
[get_ports "SMA_MGT_RX_C_P"]
[get_ports "SMA_MGT_TX_N"]
[get_ports "SMA_MGT_TX_P"]
[get_ports "USER_SMA_MGT_CLOCK_C_N"]
[get_ports "USER_SMA_MGT_CLOCK_C_P"]
[get_ports "USER_MGT_SI570_CLOCK1_C_N"]
[get_ports "USER_MGT_SI570_CLOCK1_C_P"]
[get_ports "USER_MGT_SI570_CLOCK2_C_N"]
[get_ports "USER_MGT_SI570_CLOCK2_C_P"]
[get_ports "UART2_TXD_O_FPGA_RXD"]
LVCMOS33 [get_ports "UART2_TXD_O_FPGA_RXD"]
[get_ports "UART2_RXD_I_FPGA_TXD"]
LVCMOS33 [get_ports "UART2_RXD_I_FPGA_TXD"]
[get_ports "UART2_RTS_O_B"]
LVCMOS33 [get_ports "UART2_RTS_O_B"]
[get_ports "UART2_CTS_I_B"]
LVCMOS33 [get_ports "UART2_CTS_I_B"]
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