Board Features - Xilinx ZCU102 User Manual

Board Features

The ZCU102 evaluation board features are listed here. Detailed information for each feature
is provided in Chapter 3, Board Component
• XCZU9EG-2FFVB1156I MPSoC
• PL V for range in datasheet
CCINT
• Form factor for PCIe Gen2x4 Host, Micro-ATX chassis footprint
• Configuration from QSPI
• Configuration from SD card
• Configuration over JTAG with PC4 header
• Configuration over JTAG with ARM 20-pin header
• Configuration over USB-to-JTAG Bridge
• Clocks (PL-system, PS_CLK, Programmable Clock, SMA, SMA_GT_REF, Ethernet, USB)
• PS DDR4 64-bit SODIMM w/ ECC
• PL DDR4 Component (16-bit)
• PS GTR assignment
SATA
°
DisplayPort
°
USB3
°
PCIe Gen2x4 Root Port
°
• PL GTH assignment
FMC #1 (8 GTH) and FMC #2 (8 GTH) PL GT assignment
°
HDMI (3 GTH) PL GT assignment
°
SFP+ (4 GTH) PL GT assignment
°
SMA (1 GTH) PL GT assignment
°
• PL FMC HPC #1 Connectivity - Full LA Bus
• PL FMC HPC #2 Connectivity - Partial LA Bus
• PS MIO: QSPI
• PS MIO: Ethernet
• PS MIO: USB2 (same connector as USB3)
• PS MIO: SD
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Descriptions.
www.xilinx.com
Chapter 1: Introduction
8
Send Feedback