Xilinx ZCU102 User Manual page 22

The Zynq UltraScale+ MPSoC PS block has three major processing units:
Cortex-A53 application processing unit (APU)-ARM v8 architecture-based 64-bit
°
quad-core multiprocessing CPU.
Cortex-R5 real-time processing unit (RPU)-ARM v7 architecture-based 32-bit dual
°
real-time processing unit with dedicated tightly coupled memory (TCM).
Mali-400 graphics processing unit (GPU)-graphics processing unit with pixel and
°
geometry processor and 64 KB L2 cache.
The Zynq UltraScale+ MPSoC PS has four high-speed serial I/O (HSSIO) interfaces
supporting the following protocols:
Integrated block for PCI Express® interface-PCIe™ base specification version 2.1
°
compliant.
SATA 3.1 specification compliant interface.
°
DisplayPort interface-implements a DisplayPort source-only interface with video
°
resolution up to 4K x 2K-30 (300 MHz pixel rate).
USB 3.0 interface-compliant to USB 3.0 specification implementing a 5 Gb/s line
°
rate.
Serial GMII interface-supports a 1 Gb/s SGMII interface.
°
The PS and PL can be coupled with multiple interfaces and other signals to effectively
integrate user-created hardware accelerators and other functions in the PL logic that are
accessible to the processors. They can also access memory resources in the processing
system. The PS I/O peripherals, including the static/flash memory interfaces share a
multiplexed I/O (MIO) of up to 78 MIO pins. Zynq UltraScale+ MPSoCs can also use the I/O
in the PL domain for many of the PS I/O peripherals. This is done through an extended
multiplexed I/O interface (EMIO).and boots at power-up or reset.
For additional information on Zynq UltraScale+ MPSoC devices, see the UltraScale
Architecture and Product Overview (DS890)
Technical Reference Manual (UG1085)
MPSoC configuration options.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Chapter 3:
[Ref 1], and the Zynq UltraScale+ MPSoC
[Ref 2] for more information about Zynq UltraScale+
www.xilinx.com
Board Component Descriptions
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