Xilinx ZCU102 User Manual page 31

Table 3-4: DDR4 Component Memory Connection to the XCZU9EG MPSoC (Cont'd)
XCZU9EG
(U1) Pin
AL6
AN2
The ZCU102 board DDR4 16-bit component memory interface adheres to the constraints
Note:
guidelines documented in the PCB Guidelines for DDR4 section of UltraScale Architecture PCB Design
User Guide (UG583)
implementations. Other memory interface details are also available in the UltraScale Architecture
FPGAs Memory Interface Solutions Product Guide (PG150)
MT40A256M16GE-075E data sheet at the Micron website
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Net Name I/O Standard
DDR4_DM0 POD12_DCI
DDR4_DM1 POD12_DCI
[Ref 3]. The ZCU102 DDR4 component interface is a 40Ω impedance
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Chapter 3: Board Component Descriptions
DDR4 Component Memory
Pin Number Pin Name
E7 DML_B/DBIL_B
E2 DMU_B/DBIU_B
[Ref 4]. For more details, see the Micron
[Ref 13].
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