Xilinx ZCU102 User Manual page 95

Table 3-45: J5 HPC0 FMC Section C and D Connections to XCZU9EG U1
J5 Pin Schematic Net Name
C2 FMC_HPC0_DP0_C2M_P
C3 FMC_HPC0_DP0_C2M_N
C6 FMC_HPC0_DP0_M2C_P
C7 FMC_HPC0_DP0_M2C_N
C10 FMC_HPC0_LA06_P
C11 FMC_HPC0_LA06_N
C14 FMC_HPC0_LA10_P
C15 FMC_HPC0_LA10_N
C18 FMC_HPC0_LA14_P
C19 FMC_HPC0_LA14_N
C22 FMC_HPC0_LA18_CC_P
C23 FMC_HPC0_LA18_CC_N
C26 FMC_HPC0_LA27_P
C27 FMC_HPC0_LA27_N
C30 FMC_HPC0_IIC_SCL
C31 FMC_HPC0_IIC_SDA
C34 GND
C35 VCC12_SW
C37 VCC12_SW
C39 UTIL_3V3
Notes:
1. Series capacitor coupled to XCZU9EG U1 pin.
2. Connected to I2C switch U135 pins 4 and 5.
3. XCZU9EG U1 JTAG TCK, TMS, TDO pins R25, R24, T25 are buffered by U48 SN74AVC8T245.
4. J5 HPC0 TDO-TDI connections to U27 HPC0 FMC JTAG bypass switch (N.C. normally-closed/bypassing J5 until an FMC card
is plugged onto J5).
5. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
I/O
U1 Pin J5 Pin
Standard
G4
G3
H2
H1
LVCMOS18 AC2
LVCMOS18 AC1
LVCMOS18 W5
LVCMOS18 W4
LVCMOS18 AC7
LVCMOS18 AC6
LVCMOS18 N9
LVCMOS18 N8
LVCMOS18 M10
LVCMOS18 L10
(2)
(2)
www.xilinx.com
Chapter 3:
Schematic Net Name
D1 VADJ_FMC_PGOOD
D4 FMC_HPC0_GBTCLK0_M2C_P
D5 FMC_HPC0_GBTCLK0_M2C_N
D8 FMC_HPC0_LA01_CC_P
D9 FMC_HPC0_LA01_CC_N
D11 FMC_HPC0_LA05_P
D12 FMC_HPC0_LA05_N
FMC_HPC0_LA09_P
D14
D15 FMC_HPC0_LA09_N
D17 FMC_HPC0_LA13_P
D18 FMC_HPC0_LA13_N
D20 FMC_HPC0_LA17_CC_P
D21 FMC_HPC0_LA17_CC_N
D23 FMC_HPC0_LA23_P
D24 FMC_HPC0_LA23_N
D26 FMC_HPC0_LA26_P
D27 FMC_HPC0_LA26_N
D29 FMC_HPC0_TCK_BUF
D30 FPGA_TDO_FMC_TDI_BUF
D31 FMC_HPC0_TDO_HPC1_TDI
D32 UTIL_3V3_10A
D33 FMC_HPC0_TMS_BUF (3)
D34 NC
D35 GND
D36 UTIL_3V3
D38 UTIL_3V3
D40 UTIL_3V3
Board Component Descriptions
I/O
U1 Pin
Standard
(5)
U63.32,
(1)
(1)
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
(3)
(4)
(3)(4)
Send Feedback
J4.D1,
U66.6
G8
G7
AB4
AC4
AB3
AC3
W2
W1
AB8
AC8
P11
N11
L16
K16
L15
K15
95