Xilinx ZCU102 User Manual page 88

Table 3-40 lists GTH bank 230 connections.
Table 3-40: ZCU102 GTH Bank 230 Interface Connections
XCZU9EG XCZU9EG (U1) Pin
(U1) Pin Name
MGTHTXP0_230
E4
E3 MGTHTXN0_230
D2 MGTHRXP0_230
D1 MGTHRXN0_230
MGTHTXP1_230
D6
D5 MGTHTXN1_230
C4 MGTHRXP1_230
MGTHRXN1_230
C3
B6 MGTHTXP2_230
B5 MGTHTXN2_230
B2 MGTHRXP2_230
MGTHRXN2_230
B1
A8 MGTHTXP3_230
A7 MGTHTXN3_230
A4 MGTHRXP3_230
MGTHRXN3_230
A3
C8 MGTREFCLK0P_230
C7 MGTREFCLK0N_230 USER_MGT_SI570_CLOCK2_C_N
MGTREFCLK1P_230
B10
B9 MGTREFCLK1N_230 SFP_SI5328_OUT_C_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
3. U51 buffer driven by SI570 U56 (156.250 MHz default).
For additional information on GTH transceivers, see the UltraScale Architecture GTH
Transceivers User Guide (UG576)
PCIe functionality, see the UltraScale Architecture Gen3 Integrated Block for PCI Express
LogiCORE IP Product Guide (PG156)
standard is available at the PCI Express website
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Schematic Net Name
SFP0_TX_P
SFP0_TX_N
SFP0_RX_P
SFP0_RX_N
SFP1_TX_P
SFP1_TX_N
SFP1_RX_P
SFP1_RX_N
SFP2_TX_P
SFP2_TX_N
SFP2_RX_P
SFP2_RX_N
SFP3_TX_P
SFP3_TX_N
SFP3_RX_P
SFP3_RX_N
USER_MGT_SI570_CLOCK2_C_P
SFP_SI5328_OUT_C_P (1)
(1)
[Ref 5]. For additional information about UltraScale FPGA
[Ref 6]. Additional information about the PCI Express
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected To
(2)
Pin No. Pin Name
RT_TD_P
RT18
RT19 RT_TD_N
RT13 RT_RD_P
RT12 RT_RD_N
RL_TD_P
RL18
RL19 RL_TD_N
RL13 RL_RD_P
RL_RD_N
RL12
LT18 LT_TD_P
LT19 LT_TD_N
LT13 LT_RD_P
LT_RD_N
LT12
LL18 LL_TD_P
LL19 LL_TD_N
LL13 LL_RD_P
LL_RD_N
LL12
(1) 13 Q2_P
(1)
14 Q2_N
CLKOUT1_P
28
29 CLKOUT1_N
[Ref 19].
Device
QUAD SFP P2
(3)
SI53340
BUFF. U51
SI5328B U20
88
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