Xilinx ZCU102 User Manual page 85

Table 3-37 lists GTH bank 130 connections.
Table 3-37: ZCU102 GTH Bank 130 Interface Connections
XCZU9EG XCZU9EG (U1) Pin
(U1) Pin Name
MGTHTXP0_130
F29
F30 MGTHTXN0_130
E31 MGTHRXP0_130
E32 MGTHRXN0_130
MGTHTXP1_130
D29
D30 MGTHTXN1_130
D33 MGTHRXP1_130
MGTHRXN1_130
D34
B29 MGTHTXP2_130
B30 MGTHTXN2_130
C31 MGTHRXP2_130
MGTHRXN2_130
C32
A31 MGTHTXP3_130
A32 MGTHTXN3_130
B33 MGTHRXP3_130
MGTHRXN3_130
B34
G27 MGTREFCLK0P_130
G28 MGTREFCLK0N_130 FMC_HPC1_GBTCLK0_M2C_C_N
MGTREFCLK1P_130
E27
E28 MGTREFCLK1N_130 FMC_HPC1_GBTCLK1_M2C_C_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Schematic Net Name
FMC_HPC1_DP0_C2M_P
FMC_HPC1_DP0_C2M_N
FMC_HPC1_DP0_M2C_P
FMC_HPC1_DP0_M2C_N
FMC_HPC1_DP1_C2M_P
FMC_HPC1_DP1_C2M_N
FMC_HPC1_DP1_M2C_P
FMC_HPC1_DP1_M2C_N
FMC_HPC1_DP2_C2M_P
FMC_HPC1_DP2_C2M_N
FMC_HPC1_DP2_M2C_P
FMC_HPC1_DP2_M2C_N
FMC_HPC1_DP3_C2M_P
FMC_HPC1_DP3_C2M_N
FMC_HPC1_DP3_M2C_P
FMC_HPC1_DP3_M2C_N
FMC_HPC1_GBTCLK0_M2C_C_P
FMC_HPC1_GBTCLK1_M2C_C_P
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Chapter 3: Board Component Descriptions
Connected To
(2)
Pin No. Pin Name
DP0_C2M_P
C2
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
DP1_C2M_P
A22
A23 DP1_C2M_N
A2 DP1_M2C_P
DP1_M2C_N
A3
A26 DP2_C2M_P
A27 DP2_C2M_N
A6 DP2_M2C_P
DP2_M2C_N
A7
A30 DP3_C2M_P
A31 DP3_C2M_N
A10 DP3_M2C_P
DP3_M2C_N
A11
(1) D4 GBTCLK0_M2C_P
(1)
D5 GBTCLK0_M2C_N
(1) GBTCLK1_M2C_P
B20
(1) B21 GBTCLK1_M2C_N
Device
FMC HPC1 J4
85
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