Xilinx ZCU102 User Manual page 52

CP2108 Channel 2 PL-Side UART Interface
The CP2108 channel 2 PL-side UART interface circuit is shown in
connections from XCZU9EG MPSoC U1 to CP2108 U40 via TSX0104E level shifter U52 are
listed in Table
X-Ref Target - Figure 3-15
Table 3-16: XCZU9EG U1 to CP2108 U40 Connections via L/S U52
XCZU9EG (U1)
Pin
E13
F13
D12
E12
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
3-16.
Figure 3-15: PL-Side USB UART Interface
Schematic Net Name
UART2_TXD_O_FPGA_RXD
UART2_RXD_I_FPGA_TXD
UART2_RTS_O_B
UART2_CTS_I_B
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Chapter 3:
CP2108 U40
Pin Name Pin No.
TX_2 16
RX_2 15
RTS_2
14
CTS_2 13
Board Component Descriptions
Figure 3-15. The
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